Packet switching system

Claim 2

A packet switching system comprising: a plurality of inlet circuits, each inlet circuit adapted for multiplying a cell coming in by an inlet line and for producing a time stamp to be supplied with each cell; first and second switches, said switches each having inputs connected to outputs of said plurality of inlet circuits; and a plurality of outlet circuits each having inputs connected to outputs of said first and second switches for selecting a cell to be conveyed by an outlet line from a plurality of received cells that have a same time stamp, wherein each inlet circuit further comprises means for further generating an inlet number to be co-transmitted and featuring the respective inlet circuit and a particular cell, and wherein each outlet circuit further comprises means for establishing a correct order of successive cells arriving at different instants based upon the time stamp and the inlet number.

Claim 3

The packet switching system as claimed in claim 1, wherein each outlet circuit further comprises means for storing one cell from a plurality of faultlessly transmitted cells that have a same time stamp and inlet number, means for storing the time stamp and the inlet number of the cell to be stored, and means for transferring a cell that carries an oldest stored time stamp to an assigned outlet line.

Claim 4

The packet switching system as claimed in claim 2, wherein said means for storing one cell further comprises storing a cell when the cell has arrived in a time slot, wherein the time slot depends on a transmission instant in a respective inlet circuit and further when no cell carrying the same time stamp and inlet number has been stored or a faulty cell carrying the same time stamp and inlet number has been stored.

Claim 5

The packet switching system as claimed in claim 3, wherein said means for transferring a stored cell carrying an oldest time stamp further comprises transferring a stored cell carrying the oldest time stamp lying outside the time slot to the assigned outlet line.

Claim 6

The packet switching system as claimed in claim 4, wherein said means for transferring a stored cell carrying an oldest time stamp still further comprises, in the event of a plurality of stored cells having the oldest time stamp but different inlet numbers, means for transferring the cells in a predetermined order.

Claim 7

The packet switching system as claimed in claim 2, wherein each outlet circuit further comprises (i) a status memory arrangement for storing the time stamp, the inlet number and a status of a cell, (ii) a main memory arrangement for storing an assigned cell and (iii) a control circuit for controlling the status memory arrangement and the main memory arrangement, wherein the control circuit comprises means for enabling the writing of the cell, the time stamp, the inlet number and the status of the cell if stored cells do not carry the same time stamp and inlet number, means for enabling the writing of the cell and status of the cell in the case of a stored, faulty cell that carries the same time stamp and inlet number, means for enabling the status memory arrangement to determine all main memory addresses of specific cells that lie outside the time slot, means for enabling the status memory arrangement to produce the main memory address of a stored cell that carries the oldest time stamp, and means for enabling the reading of the cell stored at the main memory address.

Claim 8

The packet switching system as claimed in claim 6, wherein the control circuit further comprises means for testing whether a cell has arrived in the time slot, and further wherein each outlet circuit further comprises a counter arrangement for applying the initial value and the final value of the time slot to the control circuit.

Claim 9

The packet switching system as claimed in claim 7, wherein the status memory arrangement further comprises a status memory (i) for storing the time stamps, the inlet numbers and the status of the cells, (ii) for making comparisons between stored and fed data, and (iii) for transferring the results of the comparisons to the control circuit.

Claim 10

The packet switching system as claimed in claim 8, wherein the status memory arrangement still further comprises a first priority decoder for determining a main memory address for a cell to be written and a multipriority decoder for determining main memory addresses for one or more cells to be read, wherein, for determining the main memory address for a cell to be written, the status memory further comprises means for producing a code word for a specific time stamp and specific inlet number and the first priority decoder comprises means for supplying a main memory address via a decoding of the code word, and wherein, for determining the main memory addresses to read one or more cells, the status memory further comprises means for producing a code word for a specific time stamp and the multipriority decoder comprises means for producing at least a main memory address via a decoding of the code word.