Patent FR516645A successfully refreshed from Google Patents.
US5777629A
Expired / Lapsed
US
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Graphics subsystem with smart direct-memory-access operation
Assignee: ZiiLabs Inc Ltd
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Filing: 1995-03-24
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Granted: 1998-07-07
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Expires: 2015-03-24
Abstract
Abstract A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.
Inventors
- 👤 David Robert Baldwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:53
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/60
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
109 words
A graphics subsystem comprising: an input buffer; one or more graphics processing units, connected to read out and operate on the contents of said input buffer, and to accordingly provide graphics data outputs; and a DMA controller comprising: a connection for an external bus; control registers write-accessible from said external bus; sequential logic connected and operable, in an indexed mode, to fetch words of data and commands from said external bus and write words so fetched into said input buffer, in dependence on commands written into said control registers, wherein successive chunks of fetched words are written to locations of said input buffer which are indicated by masking bits.
Claim 2
Dependent Claim
109 words
A graphics subsystem comprising: an input buffer; one or more graphics processing units, connected to read out and operate on the contents of said input buffer, and to accordingly provide graphics data outputs; and a DMA controller comprising: a connection for an external bus; control registers write-accessible from said external bus; sequential logic connected and operable, in an indexed mode, to fetch words of data and commands from said external bus and write words so fetched into said input buffer, in dependence on commands written into said control registers, wherein successive chunks of fetched words are written to locations of said input buffer which are indicated by masking bits.
Claim 3
Dependent Claim
25 words
The subsystem of claim 1, wherein said input buffer, all said graphics processing units, and said DMA controller are integrated into a single integrated circuit.
Claim 4
Dependent Claim
15 words
The subsystem of claim 1, wherein said graphics processing units are interconnected in a pipeline.
Claim 5
Dependent Claim
15 words
The subsystem of claim 1, wherein said graphics processing units operate in a MIMD architecture.
Claim 6
Dependent Claim
17 words
The subsystem of claim 1, wherein said graphics processing units perform various respective partial stages of rendering.
Claim 7
Dependent Claim
119 words
A graphics subsystem comprising: an input buffer comprising input registers each having an address which includes group identification address bits and also other address bits; one or more graphics processing units, connected to read out and operate on the contents of said input buffer, and to accordingly provide graphics data outputs; and a DMA controller comprising: a connection for an external bus; control registers write-accessible from said external bus; in accordance with commands found in said control registers, wherein successive chunks of fetched bits are written to ones of input registers whose group identification address bits match externally received masking bits; wherein at least some combinations of registers which are frequently accessed together have identical group identification address bits.
Claim 8
Dependent Claim
119 words
A graphics subsystem comprising: an input buffer comprising input registers each having an address which includes group identification address bits and also other address bits; one or more graphics processing units, connected to read out and operate on the contents of said input buffer, and to accordingly provide graphics data outputs; and a DMA controller comprising: a connection for an external bus; control registers write-accessible from said external bus; in accordance with commands found in said control registers, wherein successive chunks of fetched bits are written to ones of input registers whose group identification address bits match externally received masking bits; wherein at least some combinations of registers which are frequently accessed together have identical group identification address bits.
Claim 9
Dependent Claim
25 words
The subsystem of claim 6, wherein said input buffer, all said graphics processing units, and said DMA controller are integrated into a single integrated circuit.
Claim 10
Dependent Claim
15 words
The subsystem of claim 6, wherein said graphics processing units are interconnected in a pipeline.
Claim 11
Dependent Claim
15 words
The subsystem of claim 6, wherein said graphics processing units operate in a MIMD architecture.
Claim 12
Dependent Claim
17 words
The subsystem of claim 6, wherein said graphics processing units perform various respective partial stages of rendering.
Claim 13
Dependent Claim
142 words
A graphics subsystem comprising: an input buffer; one or more graphics processing units, connected to read out and operate on the contents of said input buffer, and to accordingly provide graphics data outputs; and a DMA controller comprising: a connection for an external bus; control registers write-accessible from said external bus; sequential logic connected and operable, in an indexed mode, to fetch words of data or commands from said external bus and write words so fetched into said input buffer, in any one of plural modes including: a hold mode, in which successive words are written to the same location of said input buffer; an incremental mode, in which successive words are written to incremented locations of said input buffer; and an indexed mode, in which successive words are written to locations of said input buffer which are indicated by masking bits.
Claim 14
Dependent Claim
142 words
A graphics subsystem comprising: an input buffer; one or more graphics processing units, connected to read out and operate on the contents of said input buffer, and to accordingly provide graphics data outputs; and a DMA controller comprising: a connection for an external bus; control registers write-accessible from said external bus; sequential logic connected and operable, in an indexed mode, to fetch words of data or commands from said external bus and write words so fetched into said input buffer, in any one of plural modes including: a hold mode, in which successive words are written to the same location of said input buffer; an incremental mode, in which successive words are written to incremented locations of said input buffer; and an indexed mode, in which successive words are written to locations of said input buffer which are indicated by masking bits.
Claim 15
Dependent Claim
25 words
The subsystem of claim 11, wherein said input buffer, all said graphics processing units, and said DMA controller are integrated into a single integrated circuit.
Claim 16
Dependent Claim
15 words
The subsystem of claim 11, wherein said graphics processing units are interconnected in a pipeline.
Claim 17
Dependent Claim
15 words
The subsystem of claim 11, wherein said graphics processing units operate in a MIMD architecture.
Claim 18
Dependent Claim
17 words
The subsystem of claim 11, wherein said graphics processing units perform various respective partial stages of rendering.
Claim 19
Independent Claim
97 words
A method for operating a graphics subsystem, comprising the steps of: a) using one or more graphics processing units to read out and operating on the contents of an input buffer, and accordingly to generate graphics data and provide corresponding outputs; and b) selectably operating a DMA controller to fetch words of data and commands, in an indexed mode of operation, from an external bus and write words so fetched into said input buffer, wherein successive writes of fetched words are performed to non-sequentially-adjacent locations of said input buffer which are indicated by externally received masking bits.
Claim 20
Independent Claim
97 words
A method for operating a graphics subsystem, comprising the steps of: a) using one or more graphics processing units to read out and operating on the contents of an input buffer, and accordingly to generate graphics data and provide corresponding outputs; and b) selectably operating a DMA controller to fetch words of data and commands, in an indexed mode of operation, from an external bus and write words so fetched into said input buffer, wherein successive writes of fetched words are performed to non-sequentially-adjacent locations of said input buffer which are indicated by externally received masking bits.
Claim 21
Dependent Claim
25 words
The method of claim 16, wherein said input buffer, all said graphics processing units, and said DMA controller are integrated into a single integrated circuit.
Claim 22
Dependent Claim
19 words
The method of claim 16, wherein said DMA controller comprises control registers which are write-accessible over said external bus.
Claim 23
Dependent Claim
24 words
The method of claim 16, wherein said indexed mode of operation is only one of multiple selectable modes of operation of said DMA controller.
Claim 24
Dependent Claim
15 words
The method of claim 16, wherein said graphics processing units are interconnected in a pipeline.
Claim 25
Dependent Claim
15 words
The method of claim 16, wherein said graphics processing units operate in a MIMD architecture.
Claim 26
Dependent Claim
17 words
The method of claim 16, wherein said graphics processing units perform various respective partial stages of rendering.
References Cited (Backward Citations)
US4967375A
Cited
US5392391A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |