Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions

Claim 2

In a computer processing system wherein sequences of instructions stored in a main memory are loaded into lines of an instruction cache, and transferred from said instruction cache to a processing unit for execution, wherein a line replacement algorithm is utilized to overwrite said lines of said instruction cache, a method of controlling the fetching of instructions from the main memory to the instruction cache comprising the steps of: if one of said instructions transferred from said instruction cache to said processing unit is an STOUCH instruction, fetching one or more instructions identified by said STOUCH instruction from said main memory into one or more lines of said instruction cache, wherein said one or more instructions may be executed by said processing unit; resolving one or more speculations associated with said STOUCH instruction, if each of said speculations is resolved to be valid, biasing said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, biasing said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 3

The method of claim 1, further comprising the step of: if one or more of said speculations is yet to be resolved, biasing said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm.

Claim 4

The method of claim 1, wherein said STOUCH instruction includes: an op-code field that identifies said STOUCH instruction from other instructions of said sequences of instructions stored in said main memory; an address field that points to an address within said main memory of said one or more instructions identified by said STOUCH instruction; and a condition field that specifies said one or more speculations.

Claim 5

The method of claim 3, wherein said STOUCH instruction includes a mode field that is used to interpret said condition fields.

Claim 6

The method of claim 4, wherein said mode field may be one of a first value and a second value, wherein, if said mode field has said first value, said speculations are resolved valid only if each of said speculations specified by said condition field are determined to be true, and wherein, if said mode field has said second value, said speculations are resolved valid only if one or more of said speculations specified by said condition field are determined to be false.

Claim 7

The method of claim 3, wherein said STOUCH instruction comprises 32 bits, a first portion being bits 0-5, a second portion being bits 6-10, a third portion being bits 11-15, a fourth portion being bits 16-20, a fifth portion being bits 21-30, and a sixth portion being bit 31.

Claim 8

The method of claim 6, wherein said first portion comprises said op-code field.

Claim 9

The method of claim 6, wherein said third and fourth portions comprise said address field.

Claim 10

The method of claim 6, wherein said second portion comprises said condition field.

Claim 11

The method of claim 6, wherein bit 6 of said second portion comprises said mode field.

Claim 12

The method of claim 1, wherein each of said speculations comprise a speculative outcome of a branch instruction that follows said STOUCH instruction.

Claim 13

The method of claim 11, wherein the step of resolving one or more speculations associated with said STOUCH instruction includes the steps of: initially setting a resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are not yet resolved; for each speculative branch outcome identified by said STOUCH instruction, comparing said speculative branch outcome to a branch resolution output from said processing unit, if said speculative branch outcome does not match said branch resolution, setting said status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved invalid, and if each speculative branch outcome matches the corresponding branch resolution output from said processing unit, setting said resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved valid.

Claim 14

The method of claim 1, wherein each of said speculations comprise a speculative state of a condition register field upon completing an instruction that follows said STOUCH instruction.

Claim 15

The method of claim 13, wherein the step of resolving one or more speculations associated with said STOUCH instruction includes the steps of: initially setting a resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are not yet resolved; for each speculative state of said condition register field identified by said STOUCH instruction, comparing said speculative state to an actual state of said condition register field, if said speculative state of said condition register field does not match said actual state of said condition register field, setting said status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved invalid, and if each speculative state of said condition register field matches the corresponding actual state of said condition register field, setting said resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved valid.

Claim 16

The method of claim 1, wherein said instruction cache is divided into sets associated with one or more lines, and wherein the step of biasing said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm includes the steps of: fetching a missing line from said main memory that is to be stored in said instruction cache; applying said line replacement algorithm to identify a line of said instruction cache recommended for replacement, wherein said line recommended for replacement is within the set associated with said missing line; if said line recommended for replacement contains an instruction identified by said STOUCH instruction and said speculations associated with said STOUCH instruction are resolved valid, incrementing a life counter associated with said line, wherein said life counter indicates a number of times said line has previously been recommended for replacement, if said life counter is greater than a predetermined first threshold value, replacing said line with a fetched missing line, and if said life counter is not greater than said predetermined first threshold value, returning to the step above of applying said line replacement algorithm for a subset of the set of lines associated with said line, wherein said subset excludes said line, unless if said subset is null, replacing said line with said fetched missing line.

Claim 17

The method of claim 2, wherein said instruction cache is divided into sets associated with one or more lines, and wherein the step of biasing said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm includes the steps of: fetching a missing line from said main memory that is to be stored in said instruction cache; applying said line replacement algorithm to identify a line of said instruction cache recommended for replacement, wherein said line recommended for replacement is within the set associated with said missing line; if said line recommended for replacement contains an instruction identified by said STOUCH instruction and said speculations associated with said STOUCH instruction are not yet resolved, incrementing a life counter associated with said line, wherein said life counter indicates a number of times said line has previously been recommended for replacement, if said life counter is greater than a predetermined second threshold value, replacing said line with a fetched missing line, and if said life counter is not greater than said predetermined second threshold value, returning to the step above of applying said line replacement algorithm for a subset of the set of lines associated with said line, wherein said subset excludes said line, unless if said subset is null, replacing said line with said fetched missing line.

Claim 18

The method of claim 1, further comprising the step of: upon fetching said one or more instructions identified by said STOUCH instruction from said main memory into one or more lines of said instruction cache, setting a miss bit associated with each of said one or more lines of said instruction cache; wherein the step of biasing said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm includes the steps of: fetching a missing line from said main memory that is to be stored in said instruction cache; identifying a particular line within the set associated with said missing line whose associated miss bit is set and that contains an instruction identified by said STOUCH instruction, wherein said speculations associated with said STOUCH instruction are resolved invalid; and replacing said particular line with said fetched missing line.

Claim 19

The method of claim 1, wherein said STOUCH instruction is inserted into said sequences of instructions at compile-time.

Claim 20

In a computer processing system wherein data associated with one or more instructions is stored in a main memory, loaded into lines of a data cache, and transferred from said data cache to a processing unit for execution, wherein a line replacement algorithm is utilized to overwrite said lines of said data cache, a method of controlling the fetching of data from the main memory to the data cache comprising the steps of: if an instruction loaded into said processing unit for execution is an STOUCH instruction, fetching data identified by said STOUCH instruction from said main memory into one or more lines of said data cache; resolving one or more speculations associated with said STOUCH instruction, if each of said speculations is resolved to be valid, biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 21

In a computer processing system wherein data associated with one or more instructions is stored in a main memory, loaded into lines of a data cache, and transferred from said data cache to a processing unit for execution, wherein a line replacement algorithm is utilized to overwrite said lines of said data cache, a method of controlling the fetching of data from the main memory to the data cache comprising the steps of: if an instruction loaded into said processing unit for execution is an STOUCH instruction, fetching data identified by said STOUCH instruction from said main memory into one or more lines of said data cache; resolving one or more speculations associated with said STOUCH instruction, if each of said speculations is resolved to be valid, biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 22

The method of claim 19, further comprising the step of: if one or more of said speculations is yet to be resolved, biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm.

Claim 23

The method of claim 19, wherein said STOUCH instruction includes: an op-code field that identifies said STOUCH instruction from other instructions of said sequences of instructions stored in said main memory; an address field that points to an address within said main memory of said data identified by said STOUCH instruction; and a condition field that specifies said one or more speculations.

Claim 24

The method of claim 21, wherein said STOUCH instruction includes a mode field that is used to interpret said condition fields.

Claim 25

The method of claim 22, wherein said mode field may be one of a first value and a second value, wherein, if said mode field has said first value, said speculations are resolved valid only if each of said speculations specified by said condition field are determined to be true, and wherein, if said mode field has said second value, said speculations are resolved valid only if one or more of said speculations specified by said condition field are determined to be false.

Claim 26

The method of claim 21, wherein said STOUCH instruction comprises 32 bits, a first portion being bits 0-5, a second portion being bits 6-10, a third portion being bits 11-15, a fourth portion being bits 16-20, a fifth portion being bits 21-30, and a sixth portion being bit 31.

Claim 27

The method of claim 24, wherein said first portion comprises said op-code field.

Claim 28

The method of claim 24, wherein said third and fourth portions comprise said address field.

Claim 29

The method of claim 24, wherein said second portion comprises said condition field.

Claim 30

The method of claim 24, wherein bit 6 of said second portion comprises said mode field.

Claim 31

The method of claim 19, wherein each of said speculations comprise a speculative outcome of a branch instruction that follows said STOUCH instruction.

Claim 32

The method of claim 29, wherein the step of resolving one or more speculations associated with said STOUCH instruction includes the steps of: initially setting a resolution status flag associated with said STOUCH instruction to a value indicating said speculations associated with said data identified by said STOUCH instruction are not yet resolved; for each speculative branch outcome identified by said STOUCH instruction, comparing said speculative branch outcome to a branch resolution output from said processing unit, if said speculative branch outcome does not match said branch resolution, setting said status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved invalid, and if each speculative branch outcome matches the corresponding branch resolution output from said processing unit, setting said resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved valid.

Claim 33

The method of claim 19, wherein each of said speculations comprise a speculative state of a condition register field upon completing an instruction that follows said STOUCH instruction.

Claim 34

The method of claim 31, wherein the step of resolving one or more speculations associated with said STOUCH instruction includes the steps of: initially setting a resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are not yet resolved; for each speculative state of said condition register field identified by said STOUCH instruction, comparing said speculative state to an actual state of said condition register field, if said speculative state of said condition register field does not match said actual state of said condition register field, setting said status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved invalid, and if each speculative state of said condition register field matches the corresponding actual state of said condition register field, setting said resolution status flag associated with said STOUCH instruction to a value indicating said speculations identified by said STOUCH instruction are resolved valid.

Claim 35

The method of claim 19, wherein said data cache is divided into sets associated with one or more lines, and wherein the step of biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm includes the steps of: fetching a missing line from said main memory that is to be stored in said data cache; applying said line replacement algorithm to identify a line of said data cache recommended for replacement, wherein said line recommended for replacement is within the set associated with said missing line; if said line recommended for replacement contains data identified by said STOUCH instruction and said speculations associated with said STOUCH instruction are resolved valid, incrementing a life counter associated with said line, wherein said life counter indicates a number of times said line has previously been recommended for replacement, if said life counter is greater than a predetermined first threshold value, replacing said line with a fetched missing line, and if said life counter is not greater than said predetermined first threshold value, returning to the step above of applying said line replacement algorithm for a subset of the set of lines associated with said line, wherein said subset excludes said line, unless if said subset is null, replacing said line with said fetched missing line.

Claim 36

The method of claim 20, wherein said data cache is divided into sets associated with one or more lines, and wherein the step of biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm includes the steps of: fetching a missing line from said main memory that is to be stored in said data cache; applying said line replacement algorithm to identify a line of said data cache recommended for replacement, wherein said line recommended for replacement is within the set associated with said missing line; if said line recommended for replacement contains data identified by said STOUCH instruction and said speculations associated with said STOUCH instruction are not yet resolved, incrementing a life counter associated with said line, wherein said life counter indicates a number of times said line has previously been recommended for replacement, if said life counter is greater than a predetermined second threshold value, replacing said line with a fetched missing line, and if said life counter is not greater than said predetermined second threshold value, returning to the step above of applying said line replacement algorithm for a subset of the set of lines associated with said line, wherein said subset excludes said line, unless if said subset is null, replacing said line with said fetched missing line.

Claim 37

The method of claim 19, further comprising the step of: upon fetching said one or more instructions identified by said STOUCH instruction from said main memory into one or more lines of said data cache, setting a miss bit associated with each of said one or more lines of said data cache; wherein the step of biasing said line replacement algorithm such that said one or more lines of said data cache containing said data identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm includes the steps of: fetching a missing line from said main memory that is to be stored in said data cache; identifying a particular line within the set associated with said missing line whose associated miss bit is set and that contains data identified by said STOUCH instruction, wherein said speculations associated with said STOUCH instruction are resolved invalid; and replacing said particular line with said fetched missing line.

Claim 38

The method of claim 19, wherein said STOUCH instruction is inserted into said sequences of instructions at compile-time.

Claim 39

A data processing system comprising: main memory for storing sequences of instructions and data values associated with said instructions; an instruction cache, coupled to said main memory, having lines each storing one or more instructions to be executed by a processing unit, wherein a line replacement algorithm is utilized to overwrite said lines of said instruction cache, an instruction fetch unit for fetching one or more instructions from said main memory into said instruction cache; means for recognizing an STOUCH instruction from other instructions loaded into said processing unit for execution, and, upon recognizing said STOUCH instruction, for controlling said instruction fetch unit to fetch one or more instructions identified by said STOUCH instruction from said main memory into one or more lines of said instruction cache, wherein said one or more instructions may be executed by said processing unit; and STOUCH evaluation logic that resolves one or more speculations associated with said STOUCH instruction, wherein if each of said speculations is resolved to be valid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 40

A data processing system comprising: main memory for storing sequences of instructions and data values associated with said instructions; an instruction cache, coupled to said main memory, having lines each storing one or more instructions to be executed by a processing unit, wherein a line replacement algorithm is utilized to overwrite said lines of said instruction cache, an instruction fetch unit for fetching one or more instructions from said main memory into said instruction cache; means for recognizing an STOUCH instruction from other instructions loaded into said processing unit for execution, and, upon recognizing said STOUCH instruction, for controlling said instruction fetch unit to fetch one or more instructions identified by said STOUCH instruction from said main memory into one or more lines of said instruction cache, wherein said one or more instructions may be executed by said processing unit; and STOUCH evaluation logic that resolves one or more speculations associated with said STOUCH instruction, wherein if each of said speculations is resolved to be valid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 41

The data processing system of claim 37, wherein if one or more of said speculations is yet to be resolved, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said instruction cache containing said one or more instructions identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm.

Claim 42

The data processing system of claim 37, wherein said STOUCH instruction includes: an op-code field that identifies said STOUCH instruction from other instructions of said sequences of instructions stored in said main memory; an address field that points to an address within said main memory of said one or more instructions identified by said STOUCH instruction; and a condition field that specifies said one or more speculations.

Claim 43

The data processing system of claim 39, wherein said STOUCH evaluation logic includes a buffer for storing an entry corresponding to said STOUCH instruction, wherein said entry is utilized by said STOUCH evaluation logic to evaluate said STOUCH instruction, said entry including at least a line tag and a speculation tag, wherein said line tag points to one or more lines of said instruction cache that contain said one or more instructions identified by said address field of said STOUCH instruction, and wherein said speculation tag specifies said speculations specified by said condition field of said STOUCH instruction.

Claim 44

The data processing system of claim 40, wherein said speculation tag includes a mode bit that is used by said STOUCH evaluation logic to interpret said speculations encoded by said speculation tag.

Claim 45

The data processing system of claim 41, wherein said mode bit may be one of a first value and a second value, wherein, if said mode bit has said first value, said STOUCH evaluation logic resolves said speculations as valid only if each of said speculations specified by said condition field are determined to be true, and wherein, if said mode field has said second value, said STOUCH evaluation logic resolves said speculations as valid only if on or more of said speculations specified by said condition field are determined to be false.

Claim 46

The data processing system of claim 40, wherein each of said speculations comprise a speculative outcome of a branch instruction that follows said STOUCH instruction.

Claim 47

The data processing system of claim 43, wherein said entry of said buffer corresponding to said STOUCH instruction comprises a control tag that includes at least a resolution status field, wherein said resolution status field indicates whether the speculations encoded by said speculation tag of said entry are one of: not yet resolved, resolved valid, and resolved invalid.

Claim 48

The data processing system of claim 44, wherein said STOUCH evaluation logic includes control logic that initially sets said resolution status field of said entry stored in said buffer that is associated with said STOUCH instruction to a value indicating said speculations encoded by said speculation tag of said entry are not yet resolved, for each speculative branch outcome identified by said STOUCH instruction, compares said speculative branch outcome to a branch resolution output from said processing unit, if said speculative branch outcome does not match said branch resolution, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by said speculation tag of said entry are resolved invalid, and if each speculative branch outcome matches the corresponding branch resolution output from said processing unit, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by speculation tag of said entry are resolved valid.

Claim 49

The data processing system of claim 40, wherein each of said speculations comprise a speculative state of a condition register field upon completing an instruction that follows said STOUCH instruction.

Claim 50

The data processing system of claim 46, wherein said entry of said buffer corresponding to said STOUCH instruction comprises a control tag that includes at least a resolution status field, wherein said resolution status field indicates whether the speculations encoded by said speculation tag of said entry are one of: not yet resolved, resolved valid, and resolved invalid.

Claim 51

The data processing system of claim 47, wherein said STOUCH evaluation logic includes control logic that initially sets said resolution status field of said entry associated with said STOUCH instruction to a value indicating said speculations encoded by said speculation tag of said entry are not yet resolved; for each speculative state of said condition register field encoded by said speculation tag of said entry, compares said speculative state to an actual state of said condition register field, if said speculative state does not match said actual state of said condition register field, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by said speculation tag of said entry are resolved invalid, and if each speculative state matches the corresponding actual state of said condition register field, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by said speculation tag of said entry are resolved valid.

Claim 52

The data processing system of claim 37, wherein said STOUCH instruction is inserted into said sequences of instructions at compile-time.

Claim 53

A data processing system comprising: main memory for storing sequences of instructions and data values associated with said instructions; a data cache, coupled to said main memory, having lines each storing one or more data values utilized by a processing unit in executing said instructions stored in said main memory, wherein a line replacement algorithm is utilized to overwrite said lines of said data cache, a data fetch unit for fetching data values from said main memory into said data cache; means for recognizing an STOUCH instruction from other instructions loaded into said processing unit for execution, and, upon recognizing said STOUCH instruction, for controlling said data fetch unit to fetch one or more data values identified by said STOUCH instruction from said main memory into one or more lines of said data cache; STOUCH evaluation logic that resolves one or more speculations associated with said STOUCH instruction, wherein if each of said speculations is resolved to be valid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said data cache containing said one or more data values identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said data cache containing said one or more data values identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 54

A data processing system comprising: main memory for storing sequences of instructions and data values associated with said instructions; a data cache, coupled to said main memory, having lines each storing one or more data values utilized by a processing unit in executing said instructions stored in said main memory, wherein a line replacement algorithm is utilized to overwrite said lines of said data cache, a data fetch unit for fetching data values from said main memory into said data cache; means for recognizing an STOUCH instruction from other instructions loaded into said processing unit for execution, and, upon recognizing said STOUCH instruction, for controlling said data fetch unit to fetch one or more data values identified by said STOUCH instruction from said main memory into one or more lines of said data cache; STOUCH evaluation logic that resolves one or more speculations associated with said STOUCH instruction, wherein if each of said speculations is resolved to be valid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said data cache containing said one or more data values identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm, and if any of said speculations is resolved to be invalid, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said data cache containing said one or more data values identified by said STOUCH instruction are retained for a shorter number of machine cycles than during normal operation of said line replacement algorithm.

Claim 55

The data processing system of claim 50, wherein if one or more of said speculations is yet to be resolved, said STOUCH evaluation logic biases said line replacement algorithm such that said one or more lines of said data cache containing said one or more data values identified by said STOUCH instruction are retained for a greater number of machine cycles than during normal operation of said line replacement algorithm.

Claim 56

The data processing system of claim 50, wherein said STOUCH instruction includes: an op-code field that identifies said STOUCH instruction from other instructions of said sequences of instructions stored in said main memory; an address field that points to an address within said main memory of said one or more data values identified by said STOUCH instruction; and a condition field that specifies said one or more speculations.

Claim 57

The data processing system of claim 52, wherein said STOUCH evaluation logic includes a buffer for storing an entry corresponding to said STOUCH instruction, wherein said entry is utilized by said STOUCH evaluation logic to evaluate said STOUCH instruction, said entry including at least a line tag and a speculation tag, wherein said line tag points to one or more lines of said data cache that contain said one or more data values identified by said address field of said STOUCH instruction, and wherein said speculation tag specifies said speculations specified by said condition field of said STOUCH instruction.

Claim 58

The data processing system of claim 53, wherein said speculation tag includes a mode bit that is used by said STOUCH evaluation logic to interpret said speculations encoded by said speculation tag.

Claim 59

The data processing system of claim 54, wherein said mode bit may be one of a first value and a second value, wherein, if said mode bit has said first value, said STOUCH evaluation logic resolves said speculations as valid only if each of said speculations specified by said condition field are determined to be true, and wherein, if said mode field has said second value, said STOUCH evaluation logic resolves said speculations as valid only if on or more of said speculations specified by said condition field are determined to be false.

Claim 60

The data processing system of claim 53, wherein each of said speculations comprise a speculative outcome of a branch instruction that follows said STOUCH instruction.

Claim 61

The data processing system of claim 56, wherein said entry of said buffer corresponding to said STOUCH instruction comprises a control tag that includes at least a resolution status field, wherein said resolution status field indicates whether the speculations encoded by said speculation tag of said entry are one of: not yet resolved, resolved valid, and resolved invalid.

Claim 62

The data processing system of claim 57, wherein said STOUCH evaluation logic includes control logic that initially sets said resolution status field of said entry stored in said buffer that is associated with said STOUCH instruction to a value indicating said speculations encoded by said speculation tag of said entry are not yet resolved, for each speculative branch outcome identified by said STOUCH instruction, compares said speculative branch outcome to a branch resolution output from said processing unit, if said speculative branch outcome does not match said branch resolution, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by said speculation tag of said entry are resolved invalid, and if each speculative branch outcome matches the corresponding branch resolution output from said processing unit, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by speculation tag of said entry are resolved valid.

Claim 63

The data processing system of claim 53, wherein each of said speculations comprise a speculative state of a condition register field upon completing an instruction that follows said STOUCH instruction.

Claim 64

The data processing system of claim 59, wherein said entry of said buffer corresponding to said STOUCH instruction comprises a control tag that includes at least a resolution status field, wherein said resolution status field indicates whether the speculations encoded by said speculation tag of said entry are one of: not yet resolved, resolved valid, and resolved invalid.

Claim 65

The data processing system of claim 60, wherein said STOUCH evaluation logic includes control logic that initially sets said resolution status field of said entry associated with said STOUCH instruction to a value indicating said speculations encoded by said speculation tag of said entry are not yet resolved; for each speculative state of said condition register field encoded by said speculation tag of said entry, compares said speculative state to an actual state of said condition register field, if said speculative state does not match said actual state of said condition register field, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by said speculation tag of said entry are resolved invalid, and if each speculative state matches the corresponding actual state of said condition register field, sets said resolution status field of said control tag of said entry to a value indicating said speculations encoded by said speculation tag of said entry are resolved valid.

Claim 66

The data processing system of claim 50, wherein said STOUCH instruction is inserted into said sequences of instructions at compile-time.