Linear amplifier system and method

Claim 2

A linearized amplifier system, comprising: an input port for receiving an input signal; a signal amplifier for amplifying said input signal into an amplified signal, said signal amplifier having an input and an output and a signal amplifier transfer characteristic between said input and said output; a signal predistortor arranged in series with said signal amplifier to couple said input port with said signal amplifier input, said signal predistortor configured to have a signal predistortor transfer characteristic which provides a signal transfer characteristic for the series combination of said signal predistortor and said signal amplifier that is more linear than said signal amplifier transfer characteristic; an output port for receiving said amplified signal; a first delay element coupled between said input port and said signal amplifier output; a second delay element connecting said signal amplifier output and said output port; and an error amplifier arranged in parallel with said second delay element to couple said signal amplifier output with said output port; said signal predistortor, said signal amplifier and said first delay element forming an error sensor loop for comparing a sample of said amplified signal with a sample of said input signal to generate an error signal representative of errors in said amplified signal caused by nonlinearities in said signal transfer characteristic; and said second delay element and said error amplifier forming an error correction loop for coupling said error signal into said output port for cancellation of at least a portion of said errors.

Claim 3

The linearized amplifier system of claim 1, wherein said error amplifier has an error amplifier transfer characteristic and further including an error predistortor arranged in series with said error amplifier wherein said error predistortor has an error predistortor transfer characteristic which is configured to provide an error transfer characteristic for the series combination of said error predistortor and said error amplifier which is more linear than said error amplifier transfer characteristic.

Claim 4

The linearized amplifier system of claim 1, wherein said signal predistortor includes: a first amplifier; a second amplifier arranged in parallel with said first amplifier; a phase shifter having a selectable phase shift and arranged in series with one of said first and second amplifiers; and an attenuator having a selectable attenuation and arranged in series with the other of said first and second amplifiers.

Claim 5

The linearized amplifier system of claim 1, further including a signal coupling structure arranged to couple to said signal amplifier output, said first delay element and said error amplifier for receiving a sample of said amplified signal and a sample of said input signal and generating said error.

Claim 6

The linearized amplifier system of claim 1, further including; an adjustable signal attenuator; and an adjustable signal phase shifter, said adjustable signal attenuator and said adjustable signal phase shifter arranged in series with said signal amplifier to facilitate changes in the amplitude and phase of said input signal sample.

Claim 7

The linearized amplifier system of claim 5, wherein said error amplifier has an output coupled to said output port and further including: a generator arranged to couple a first tone signal with a first tone frequency into said input port; a detector coupled to said error amplifier output to generate a detector signal representative of the amplitude of a signal having said first tone frequency; and a controller arranged to receive said detector signal and configured to adjust at least one of said adjustable signal attenuator and said adjustable signal phase shifter to reduce the amplitude of said detector signal.

Claim 8

The linearized amplifier system of claim 1, further including; an adjustable error attenuator; and an adjustable error phase shifter, said adjustable error attenuator and said adjustable error phase shifter arranged in series with said error amplifier to facilitate changes in the amplitude and phase of said error signal which enhance said cancellation.

Claim 9

The linearized amplifier system of claim 7, wherein said error amplifier has an output coupled to said output port and further including: a generator arranged to couple a second tone signal with a second tone frequency into said signal amplifier input; a detector coupled to said output port to generate a detector signal representative of the amplitude of a signal having said second tone frequency; and a controller arranged to receive said detector signal and configured to adjust at least one of said adjustable error attenuator and said adjustable error phase shifter to reduce the amplitude of said detector signal.

Claim 10

The linearized amplifier system of claim 1, wherein said signal predistortor is configured to permit adjustment of said signal predistortor transfer characteristic to accommodate changes in said signal amplifier transfer characteristic.

Claim 11

The linearized amplifier system of claim 1, wherein said signal amplifier is a traveling-wave-tube amplifier.

Claim 12

A linearized amplifier system, comprising: an input port for receiving an input signal; a signal amplifier for amplifying said input signal into an amplified signal, said signal amplifier having an input and an output and a signal amplifier transfer characteristic between said input and said output, said amplifier input coupled to said input port; an output port for receiving said amplified signal; a first delay element coupled between said input port and said signal amplifier output; a second delay element connecting said signal amplifier output and said output port; an error amplifier having an error amplifier transfer characteristic; and an error predistortor arranged in series with said error amplifier, said error predistortor configured to have an error predistortor transfer characteristic which provides an error transfer characteristic for the series combination of said error predistortor and said error amplifier that is more linear than said error amplifier transfer characteristic, said error predistortor and said error amplifier arranged in parallel with said second delay element to couple said signal amplifier output with said output port; said signal amplifier and said first delay element forming an error sensor loop for comparing a sample of said amplified signal with a sample of said input signal to generate an error signal representative of errors in said amplified signal caused by nonlinearities in said signal transfer characteristic; and said second delay element, said error predistortor and said error amplifier forming an error correction loop for coupling said error signal into said output port for cancellation of at least a portion of said errors.

Claim 13

A linearized amplifier system, comprising: an input port for receiving an input signal; a signal amplifier for amplifying said input signal into an amplified signal, said signal amplifier having an input and an output and a signal amplifier transfer characteristic between said input and said output, said amplifier input coupled to said input port; an output port for receiving said amplified signal; a first delay element coupled between said input port and said signal amplifier output; a second delay element connecting said signal amplifier output and said output port; an error amplifier having an error amplifier transfer characteristic; and an error predistortor arranged in series with said error amplifier, said error predistortor configured to have an error predistortor transfer characteristic which provides an error transfer characteristic for the series combination of said error predistortor and said error amplifier that is more linear than said error amplifier transfer characteristic, said error predistortor and said error amplifier arranged in parallel with said second delay element to couple said signal amplifier output with said output port; said signal amplifier and said first delay element forming an error sensor loop for comparing a sample of said amplified signal with a sample of said input signal to generate an error signal representative of errors in said amplified signal caused by nonlinearities in said signal transfer characteristic; and said second delay element, said error predistortor and said error amplifier forming an error correction loop for coupling said error signal into said output port for cancellation of at least a portion of said errors.

Claim 14

The linearized amplifier system of claim 11, wherein said signal amplifier has a signal amplifier transfer characteristic and further including a signal predistortor arranged in series with said signal amplifier wherein said signal predistortor is configured to have a signal predistortor transfer characteristic which provides a signal transfer characteristic for the series combination of said signal predistortor and said signal amplifier that is more linear than said signal amplifier transfer characteristic.

Claim 15

The linearized amplifier system of claim 11, wherein said error predistortor includes: a first amplifier; a second amplifier arranged in parallel with said first amplifier; a phase shifter having a selectable phase shift and arranged in series with one of said first and second amplifiers; and an attenuator having a selectable attenuation and arranged in series with the other of said first and second amplifiers.

Claim 16

The linearized amplifier system of claim 11, further including a signal coupling structure arranged to couple to said signal amplifier output, said first delay element and said error amplifier for receiving a sample of said amplified signal and a sample of said input signal and generating said error.

Claim 17

The linearized amplifier system of claim 11, further including; an adjustable signal attenuator; and an adjustable signal phase shifter, said adjustable signal attenuator and said adjustable signal phase shifter arranged in series with said signal amplifier to facilitate changes in the amplitude and phase of said input signal sample.

Claim 18

The linearized amplifier system of claim 15, wherein said error amplifier has an output coupled to said output port and further including: a generator arranged to couple a first tone signal with a first tone frequency into said input port; a detector coupled to said error amplifier output to generate a detector signal representative of the amplitude of a signal having said first tone frequency; and a controller arranged to receive said detector signal and configured to adjust at least one of said adjustable signal attenuator and said adjustable signal phase shifter to reduce the amplitude of said detector signal.

Claim 19

The linearized amplifier system of claim 11, further including; an adjustable error attenuator; and an adjustable error phase shifter, said adjustable error attenuator and said adjustable error phase shifter arranged in series with said error amplifier to facilitate changes in the amplitude and phase of said error signal which enhance said cancellation.

Claim 20

The linearized amplifier system of claim 17, wherein said error amplifier has an output coupled to said output port and further including: a generator arranged to couple a second tone signal with a second tone frequency into said signal amplifier input; a detector coupled to said output port to generate a detector signal representative of the amplitude of a signal having said second tone frequency; and a controller arranged to receive said detector signal and configured to adjust at least one of said adjustable error attenuator and said adjustable error phase shifter to reduce the amplitude of said detector signal.

Claim 21

The linearized amplifier system of claim 11, wherein said error predistortor is configured to permit adjustment of said error predistortor transfer characteristic to accommodate changes in said error amplifier transfer characteristic.