US5771345A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated digital processing device and method for examining the operation thereof
Assignee: Tektronix Inc
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Filing: 1996-04-25
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Granted: 1998-06-23
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Expires: 2016-04-25
Abstract
Abstract An integrated digital processing device and method for examining the operation thereof. An integrated multiple digital processing device has externally-accessible tag connections which provide signals representative of what circuit has access to external memory used by the processing device. The processing device includes a plurality of digital processor circuits, a DRAM refresh logic circuit, externally-accessible connections for receiving memory access signals from an external processor, and an arbitration circuit for determining which of the digital processor circuits, refresh logic circuit or external processor may have access to the external memory. The signals on the tag connections are provided by the arbitration circuit, and indicate which of the aforementioned circuits has access to the external memory at any moment. Preferably, an M-to-N line encoder is provided between the arbitration circuit and the externally-accessible tag connections to minimize the number of tag connections required to identify the circuit having access to the external memory.
Inventors
- 👤 James L. Tallman
- 👤 John Dierks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663; G01; G01R; G01R13/00; G01R13/20; G01R13/22; G01R13/34; G01R13/345
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
80 words
An integrated digital processing device adapted to communicate with external memory, comprising: a plurality of digital processor circuits disposed within said integrated digital processing device; and a memory access arbitration circuit for determining which of said plurality of digital processor circuits is to have access to said external memory; wherein, said arbitration circuit includes at least one externally-accessible tag line for providing signals representative of which of said plurality of digital processor circuits currently has access to said external memory.
Claim 2
Dependent Claim
80 words
An integrated digital processing device adapted to communicate with external memory, comprising: a plurality of digital processor circuits disposed within said integrated digital processing device; and a memory access arbitration circuit for determining which of said plurality of digital processor circuits is to have access to said external memory; wherein, said arbitration circuit includes at least one externally-accessible tag line for providing signals representative of which of said plurality of digital processor circuits currently has access to said external memory.
Claim 3
Dependent Claim
42 words
The processing device of claim 1, further comprising a dynamic random access memory (DRAM) refresh circuit, said external memory being dynamic random access memory (DRAM), and wherein, access to said external memory by said refresh circuit is determined by said arbitration circuit.
Claim 4
Dependent Claim
45 words
The processing device of claim 2, wherein, said arbitration circuit includes at least one externally-accessible processor connection for receiving external memory access signals from an external digital processor circuit, access to said external memory by said external processor circuit being determined by said arbitration circuit.
Claim 5
Dependent Claim
26 words
The processing device of claim 2, wherein, said arbitration circuit includes externally-accessible memory connections for conveying memory address, data and control signals to said external memory.
Claim 6
Dependent Claim
45 words
The processing device of claim 1, wherein, said arbitration circuit includes at least one externally-accessible processor connection for receiving external memory access signals from an external digital processor circuit, access to said external memory by said external processor circuit being determined by said arbitration circuit.
Claim 7
Dependent Claim
26 words
The processing device of claim 1, wherein, said arbitration circuit includes externally-accessible memory connections for conveying memory address, data and control signals to said external memory.
Claim 8
Dependent Claim
123 words
An integrated digital processing device adapted to communicate with external memory, comprising: a plurality of digital processor circuits; a memory access arbitration circuit for determining which of said plurality of digital processor circuits is to have access to said external memory; wherein, said arbitration circuit includes M tag lines for providing signals representative of which of said plurality of digital processor circuits currently has access to said external memory; and an M-to-N line encoder having an input coupled to said M tag lines of said arbitration circuit and an output comprising N externally-accessible tag connections so as to reduce the number of tag connections necessary to determine which circuit has access to said external memory from M in number to N in number.
Claim 9
Dependent Claim
123 words
An integrated digital processing device adapted to communicate with external memory, comprising: a plurality of digital processor circuits; a memory access arbitration circuit for determining which of said plurality of digital processor circuits is to have access to said external memory; wherein, said arbitration circuit includes M tag lines for providing signals representative of which of said plurality of digital processor circuits currently has access to said external memory; and an M-to-N line encoder having an input coupled to said M tag lines of said arbitration circuit and an output comprising N externally-accessible tag connections so as to reduce the number of tag connections necessary to determine which circuit has access to said external memory from M in number to N in number.
Claim 10
Independent Claim
145 words
A method for examining the operation of a digital processing system including an integrated digital processing device adapted to communicate with an external memory and having a plurality of digital processor circuits and a memory access arbitration circuit for determining which of said plurality of circuits is to have access to said external memory, and an external memory circuit connected through external memory connections to said digital processing device, said method comprising the steps of: providing tag connections to said arbitration circuit which are accessible external to said processing device and carry signals representative of which circuit has access to said external memory; detecting signals on said tag connections to determine which circuit currently has access to said external memory; and detecting signals on said external memory connections to observe memory address and data information accessed by said circuit currently having access to said memory.
Claim 11
Independent Claim
145 words
A method for examining the operation of a digital processing system including an integrated digital processing device adapted to communicate with an external memory and having a plurality of digital processor circuits and a memory access arbitration circuit for determining which of said plurality of circuits is to have access to said external memory, and an external memory circuit connected through external memory connections to said digital processing device, said method comprising the steps of: providing tag connections to said arbitration circuit which are accessible external to said processing device and carry signals representative of which circuit has access to said external memory; detecting signals on said tag connections to determine which circuit currently has access to said external memory; and detecting signals on said external memory connections to observe memory address and data information accessed by said circuit currently having access to said memory.
Claim 12
Dependent Claim
15 words
The method of claim 8, wherein said detecting is performed using a logic analyzer apparatus.
Claim 13
Dependent Claim
21 words
The method of claim 9, further comprising providing data detected by said logic analyzer apparatus to another computer for further processing.
References Cited (Backward Citations)
US5317711A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-22 | 2001-12-22 | 2002-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-22 | 2005-12-22 | 2006-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-22 | 2009-12-22 | 2010-06-23 | $7700.00 | Window Closed / Lapsed |