Device and method for display centering of the effective screen of LCD

Claim 2

A display driving device which positions an image on a liquid crystal display having a number of screen lines, said display driving device comprising: a horizontal pulse generator which receives a data enable signal and outputs a gate clock signal having a pulse frequency according to a logic state of said data enable signal, said gate clock signal controlling a start time of each of said screen lines of data displayed on said liquid crystal display; and a start pulse generator which receives said gate clock signal and a vertical synchronizing pulse and outputs a gate start pulse based on said gate clock signal and said vertical synchronizing pulse, said gate start pulse controlling a starting line among said screen lines to begin displaying said image on said liquid crystal display.

Claim 3

A display driving device according to claim 1, further comprising: a first pulse generator which generates a first horizontal pulse signal having a first pulse frequency; and a second pulse generator which generates a second horizontal pulse signal having a second pulse frequency different from said first pulse frequency, said horizontal pulse generator receiving and summing said first and second horizontal pulse signals according to said logic state of said data enable signal to produce said gate clock signal.

Claim 4

A display driving device according to claim 2, wherein said first pulse frequency is twice said second pulse frequency.

Claim 5

A display driving device according to claim 3, wherein said start pulse generator outputs said gate start pulse such that said image is centered on said liquid crystal display.

Claim 6

A display driving device according to claim 4, wherein said start pulse generator includes: a counter which counts pulses of said gate clock signal received after said vertical synchronizing pulse is received, and outputs a pulse count; and a comparator which compares said pulse count with a start count value, said start pulse generator outputting said gate start pulse when said pulse count equals said start count value.

Claim 7

A display driving device according to claim 5, wherein said start count value is determined according to an equation given by: S=(M-N)/2 wherein S is said start count value, M is said number of screen lines, and N is a number of gate lines said image.

Claim 8

A display driving device according to claim 2, wherein blank data is displayed on said screen lines according to said first frequency and image data is displayed on said screen lines according to said second frequency.

Claim 9

A driving device for positioning an image on a screen of a liquid crystal display, comprising: a first counter and a second counter which count the pulses of a received main clock and output first and second counted values, respectively; a first parallel comparator which simultaneously outputs a first pulse signal and resets said first counter when said first counted value output from said first counter equals a first predetermined value; a second parallel comparator which simultaneously outputs a second pulse signal and resets said second counter when said second counted value output from said second counter equals a second predetermined value; a first logic gate and a second logic gate which receive said first and second pulse signals, respectively, and output said first and second pulse signals, respectively, according to a logic state of a data enable signal; a summing gate which generates and outputs a gate clock by logically summing said first and second pulse signals from said first and second logic gates, respectively; a third counter which counts pulses of said gate clock input from said summing gate and outputs a third counted value; a third parallel comparator which generates and outputs a gate start pulse and simultaneously resets said third counter when said third counted value equals a third predetermined value.

Claim 10

A driving device for positioning an image on a screen of a liquid crystal display, comprising: a first counter and a second counter which count the pulses of a received main clock and output first and second counted values, respectively; a first parallel comparator which simultaneously outputs a first pulse signal and resets said first counter when said first counted value output from said first counter equals a first predetermined value; a second parallel comparator which simultaneously outputs a second pulse signal and resets said second counter when said second counted value output from said second counter equals a second predetermined value; a first logic gate and a second logic gate which receive said first and second pulse signals, respectively, and output said first and second pulse signals, respectively, according to a logic state of a data enable signal; a summing gate which generates and outputs a gate clock by logically summing said first and second pulse signals from said first and second logic gates, respectively; a third counter which counts pulses of said gate clock input from said summing gate and outputs a third counted value; a third parallel comparator which generates and outputs a gate start pulse and simultaneously resets said third counter when said third counted value equals a third predetermined value.

Claim 11

The driving device of claim 8, wherein said first logic gate further comprises an inverter which reverses said data enable signal.

Claim 12

The driving device of claim 8, wherein said first logic gate and said second logic gate are comprised of AND gate elements.

Claim 13

The driving device of claim 8, wherein said summing gate is comprised of OR gate elements.

Claim 14

The driving device of claim 8 wherein said second predetermined value is twice said first predetermined value.

Claim 15

The driving device of claim 8 wherein said third predetermined value satisfies an equation given by: ##EQU2## wherein PV 3 is said third predetermined value, M is a number of screen lines, and N is a number of gate lines in said image.

Claim 18

The method according to claim 14, wherein said step of generating said gate clock signal includes the steps of: determining said logic state of said data enable signal; outputting said first pulse signal when said data enable signal has a first logic state; and outputting said second pulse signal when said data enable signal has a second logic state.

Claim 19

The method according to claim 14 wherein said step of determining said starting line includes the steps of: counting a number of pulses in said gate clock signal since said vertical synchronizing pulse was received; and comparing said number of pulses with a predetermined value.