Timer that provides both surveying and counting functions

Claim 2

A timer which provides both surveying and counting functions comprising: a counter, a multiplexer, an edge-triggered controller, a time-base latching circuit and a pulse-detecting circuit; said multiplexer being provided with input terminals to receive signal from a system clock and output triggering signal from said edge-triggered controller; said pulse-detecting circuit being provided with input terminals to receive a sampling signal and said output triggering signal from said edge triggered controller; said pulse-detecting circuit being provided with an output terminal for sending out an enabling signal to be transmitted to said time-base latching circuit; said multiplexer also being provided with an output terminal for sending a clock signal to said time-base latching circuit; said time-base latching circuit being connected with said counter to generate an output required.

Claim 3

The timer which provides both surveying and counting functions as claimed in claim 1, wherein said pulse-detecting circuit includes a positive edge-detecting circuit, a negative edge-detecting circuit, a starting register, and a RS latching circuit; said output triggering signal and said sampling signal being sent to said positive edge-detecting circuit, and said negative edge-detecting circuit, and output thereof being transmitted to said RS latching circuit; said starting register being provided with input terminals for receiving a starting signal and a stop signal, wherein said stop signal being sent from output terminal of said negative edge-detecting circuit; said starting register being provided with means for sending out an ON/OFF signal; and said ON/OFF signal being sent to said RS latching circuit to generate said enabling signal.

Claim 4

The timer which provides both surveying and counting functions as claimed in claim 2, wherein said positive edge-detecting circuit includes D-type flip-flop, logic NOT gate and AND gate.

Claim 5

The timer which provides both surveying and counting functions as claimed in claim 2 wherein said negative edge-detecting circuit include D-type flip-flop, logic NOT gate and AND gate.

Claim 6

The timer which provides both surveying and counting functions as claimed in claim 2, wherein said starting register is a RS flip-flop.

Claim 7

The timer which provides both surveying and counting functions as claimed in claim 1, wherein said time-base latching circuit is a D-type latching circuit.

Claim 8

A timer which provides the functions of both surveying and counting, comprising: a system clock; an external signal; a sampling signal; a counter; a multiplexer; an edge-triggered controller; a time-base latching circuit; and a pulse-detecting circuit; wherein said multiplexer being provided with input terminals which are connected to said system clock to receive a system clock therefrom and to said edge-triggered controller to receive an external triggering signal therefrom; said multiplexer further being provided with means for encoding and thus producing an output signal which can be either said system clock or said external triggering signal, or both, so as to provide three different modes of operations; said edge-triggered controller being provided with input terminals for receiving said external signal and a control signal select for encoding the phase of said external signal to generate said external triggering signal, which is sent to said multiplexer and said pulse-detecting circuit; said pulse-detecting circuit being provided with input terminals which are connected to receive said sampling signal and said external triggering signal, and means for generating and sending an enabling signal to said time-base latching circuit; said time-base latching circuit being provided with input terminals to receive the output from said multiplexer and said enabling signal from said pulse-detecting circuit, and means for generating and sending an output signal to said counter.

Claim 9

A timer which provides the functions of both surveying and counting, comprising: a system clock; an external signal; a sampling signal; a counter; a multiplexer; an edge-triggered controller; a time-base latching circuit; and a pulse-detecting circuit; wherein said multiplexer being provided with input terminals which are connected to said system clock to receive a system clock therefrom and to said edge-triggered controller to receive an external triggering signal therefrom; said multiplexer further being provided with means for encoding and thus producing an output signal which can be either said system clock or said external triggering signal, or both, so as to provide three different modes of operations; said edge-triggered controller being provided with input terminals for receiving said external signal and a control signal select for encoding the phase of said external signal to generate said external triggering signal, which is sent to said multiplexer and said pulse-detecting circuit; said pulse-detecting circuit being provided with input terminals which are connected to receive said sampling signal and said external triggering signal, and means for generating and sending an enabling signal to said time-base latching circuit; said time-base latching circuit being provided with input terminals to receive the output from said multiplexer and said enabling signal from said pulse-detecting circuit, and means for generating and sending an output signal to said counter.

Claim 10

The timer which provides the functions of both surveying and counting according to claim 7 wherein: said pulse detecting circuit comprises a positive edge-detecting circuit, a negative edge-detecting circuit, a starting register, and an RS latching circuit; said external triggering signal and said sampling signal being sent to input terminals of both said positive edge-detecting circuit and said negative edge-detecting circuit; said positive edge-detecting circuit and said negative edge-detecting circuit generate outputs which are sent to said RS latching circuit; said starting register is connected to a starting signal and a stop signal, said stop signal being sent from said negative edge-detecting circuit; said starting register contains means to generate and send an ON/OFF signal to said RS latching circuit; said RS latching circuit contains means to generate said enabling signal for said pulse-detecting circuit.