Process of fabricating NAND-structure flash EEPROM using liquid phase deposition

Claim 1

A process of fabricating a flash EEPROM on a semiconductor substrate of a first conductivity type, comprising the following steps of: (a) forming a tunnel dielectric layer on the substrate; (b) forming a first conductive layer on said tunnel dielectric layer; (c) forming a plurality of mask lines on said first conductive layer; (d) etching to form a plurality of trenches by using said mask lines as a mask, said first conductive layer being etched to form a plurality of conductive lines; (e) using said mask lines as a mask to deposit isolating dielectrics in said trenches by liquid phase deposition; (f) removing said mask lines; (g) forming a gate dielectric layer on said isolating dielectrics and said conductive lines; (h) forming a second conductive layer on said gate dielectric layer; (i) patterning said second conductive layer, gate dielectric layer and conductive lines so that said remaining second conductive layer forms a plurality of control gates, and said remaining conductive lines form floating gates; and (j) implanting impurities of a second conductivity type into the substrate by using said control/floating gates as a mask to form source/drain regions.