Signal distribution apparatus for a directional signal transmission system

Claim 2

A signal distribution apparatus comprising: a plurality of signal sources for generating signals having contents that change with time and having lengths that are different from each other; a plurality of unit memory circuits U for storing a specific time period of the output of said signal sources; a memory circuit group A formed by connecting said plurality of unit memory circuits U serially; and, an electronic exchanger for sending the output of an arbitrary unit memory circuit Un in said memory circuit group A to a plurality of terminal receivers.

Claim 3

The signal distribution apparatus of claim 1, further comprising: a plurality of memory circuit groups A connected serially.

Claim 4

The signal distribution apparatus of claim 1, further comprising: a plurality of memory circuit groups A having a plurality of unit memory circuits Ui connected serially; and, a control circuit for connecting a plurality of said memory circuit groups A serially when z>q so that the memory time becomes longer than zT sec, here, qT sec is the capacity of one memory circuit group A, zT sec is the length of the signal supplied from a signal source.

Claim 5

The signal distribution apparatus of claim 1, further comprising: a plurality of memory circuit groups A; and, a judging means for judging frequently used signal sources among said plurality of signal sources; wherein, the signal sources judged as frequently used are preferentially connected to a part of said plurality of memory circuit groups A.

Claim 6

The signal distribution apparatus of claim 1, wherein said plurality of unit memory circuits include the same components.

Claim 7

The signal distribution apparatus of claim 1, further comprising: a read out control circuit for, writing the first T seconds of a signal time serially output from said signal source from a time t0 in a first unit memory circuit U1, during a next interval from t0+T seconds to t0+2T seconds, reading the first T second signal from said first unit memory circuit U1 and writing the first T second signal to a second unit memory circuit U2 and, at the same time, writing the signal from said signal source into said first unit memory circuit U1 after the first T second signal is read, during a next interval from t0+2T seconds to t0+3T seconds, reading the second T second signal from said first unit memory circuit U1 and writing the second T second signal to a second unit memory circuit U2 and, at the same time, writing the signal from said signal source in said first unit memory circuit U1 after the second T second signal is read, and, at the same time, reading the first T second signal from said second unit memory circuit U2 and writing the first T second signal in a third unit memory circuit U3, and continuing the reading and writing until the signal from the signal source is written in each of the unit memory circuits Ui, wherein, said electronic exchanger reads out the signals from the unit memory circuits U simultaneously and supplies the signal input to the first unit memory circuit U1 or a signal having the same delay, to a first terminal receiver that requests a signal from said signal source, said electronic exchanger supplies the output signal of unit memory circuit Uk+1 to the Nth terminal requesting the signal of the signal source from the beginning at the time delayed by Y seconds from the request time of the first terminal.

Claim 8

The signal distribution apparatus of claim 6, wherein the first part of the output of the signal source is supplied from time Y+p seconds, where Y>>p, to terminal N requesting the signal at a time delayed by Y seconds from the request time of the first terminal after the request by the Nth terminal Y seconds after the request by the first terminal, and connects the signal from the signal source delayed by Y seconds to said Nth terminal.

Claim 9

The signal distribution apparatus of claim 6, wherein, wherein the length of the signal from the signal source is GT seconds and when X>G, lack of signal data is stored in the unit memory circuits in the memory circuit groups A for (XT-GT) seconds.

Claim 10

The signal distribution apparatus of claim 8, further comprising: detecting means for detecting an end signal of the signal from the signal source of time length GT; wherein after the end signal is detected, lack of signal data is stored in the unit memory circuits in memory circuit groups A.

Claim 11

The signal distribution apparatus of claim 6, further comprising: a control circuit provided between said electronic exchanger and said signal source for managing which unit memory circuit is outputting the beginning of the video signal of said signal source, and, wherein said electronic exchanger supplies the beginning of the video signal of said signal source immediately or just memory circuit groups A so as to supply the requested signals from the beginning with a delay from the request time for the signal.

Claim 12

The signal distribution apparatus of claim 1, further comprising: a plurality of signal sources; a plurality of memory circuit groups A composed of a plurality of said unit memory circuits U serially connected; a control computer for sending a signal corresponding to the requests from terminals when send requests for the same signal at different times are received from a plurality of terminals under the condition of N>X, where N is the number of said signal sources, and X is the number of said memory circuit groups A, and for combining a plurality of memory circuit groups A to send the signal corresponding to the requests when the length of the signal of the signal source is longer than the memory capacity of a memory circuit group A; and, a switch group for serially connecting a number of said memory circuit groups A corresponding to the length of the source signal when a plurality of signal sources are requested from different terminal groups at the same time or at different times, and for connecting the electronic exchanger, signal sources, and memory circuit groups A so as to supply the requested signals from the beginning with a delay from the request time for the signal.

Claim 13

A signal distribution apparatus comprising: a first signal source for generating a time serial signal; a plurality of unit memory circuits for storing the output of said first signal source by time serially allotting divided intervals of the output a of said first signal source to each of the plurality of unit memory circuits; a second signal source formed by connecting said plurality of unit memory circuits; and, an electronic exchanger for sending the output of an arbitrary unit memory circuit in said second signal source to a plurality of terminal receivers; wherein said time serial signal is read from said second signal source and distributed by said electronic exchanger.

Claim 14

A signal distribution apparatus comprising: a first signal source for generating a time serial signal; a plurality of unit memory circuits for storing the output of said first signal source by time serially allotting divided intervals of the output a of said first signal source to each of the plurality of unit memory circuits; a second signal source formed by connecting said plurality of unit memory circuits; and, an electronic exchanger for sending the output of an arbitrary unit memory circuit in said second signal source to a plurality of terminal receivers; wherein said time serial signal is read from said second signal source and distributed by said electronic exchanger.

Claim 15

The signal distribution apparatus of claim 12, wherein said plurality of unit memory circuits include the same components.

Claim 16

The signal distribution apparatus of claim 12, further comprising: a read out control circuit for, writing the first T seconds of a signal time serially output from said signal source from a time t0 in a first unit memory circuit U1, during a next interval from t0+T seconds to t0+2T seconds, reading the first T second signal from said first unit memory circuit U1 and writing the first T second signal to a second unit memory circuit U2 and, at the same time, writing the signal from said signal source into said first unit memory circuit U1 after the first T second signal is read, during a next interval from t0+2T seconds to t0+3T seconds, reading the second T second signal from said first unit memory circuit U1 and writing the second T second signal to a second unit memory circuit U2 and, at the same time, writing the signal from said signal source in said first unit memory circuit U1 after the second T second signal is read out, and, at the same time, reading the first T second signal from said second unit memory circuit U2 and writing the first T second signal in a third unit memory circuit U3, and continuing the reading and writing until the signal from the signal source is written in each of the unit memory circuits Ui, wherein, said electronic exchanger reads the signals from the unit memory circuits U simultaneously and supplies the signal input to the first unit memory circuit U1 or a signal having the same delay, to a first terminal receiver that requests a signal from said signal source, said electronic exchanger supplies the output signal of unit memory circuit Uk+1 to the Nth terminal requesting the signal of the signal source from the beginning at the time delayed by Y seconds from the request time of the first terminal.

Claim 17

The signal distribution apparatus of claim 14, wherein the first part of the output of the signal source is supplied from time Y+p seconds, where Y>>p, to terminal N requesting the signal at a time delayed by Y seconds from the request time of the first terminal.

Claim 18

The signal distribution apparatus of claim 14, wherein the length of the signal from the signal source is GT seconds and when X>G, lack of signal data is stored in the unit memory circuits in the memory circuit groups A for (XT-GT) seconds.

Claim 19

The signal distribution apparatus of claim 16, further comprising: detecting means for detecting an end signal of the signal from the signal source of time length GT; wherein after the end signal is detected, lack of signal data is stored in the unit memory circuits in memory circuit groups A.

Claim 20

The signal distribution apparatus of claim 14, further comprising: a control circuit provided between said electronic exchanger and said signal source for managing which unit memory circuit is outputting the beginning of the video signal of said signal source, and, wherein said electronic exchanger supplies the beginning of the video signal of said signal source immediately or just after the request by the Nth terminal Y seconds after the request by the first terminal, and connects the signal from the signal source delayed by Y seconds to said Nth terminal.

Claim 21

The signal distribution apparatus of claim 12, wherein the time serial signal from the signal source is time serially divided and written into a plurality of said unit memory circuits in the order of first unit memory circuit to last unit memory circuit, said electronic exchanger supplies the memory contents of said plurality of unit memory circuits, in the order of first unit memory circuit to last unit memory circuit, to the first terminal receiver and the terminals requesting the time serial signal at the same time as the first terminal, said electronic exchanger also supplies the memory contents of said plurality of unit memory circuits, in the order of said first unit memory circuit to the last unit memory circuit, to the Nth terminal requesting the signal of the signal source from the beginning at a time delayed T seconds from the request by the first terminal.

Claim 22

The signal distribution apparatus of claim 12, further comprising: a plurality of signal sources; a plurality of memory circuit groups A composed of a plurality of said unit memory circuits U serially connected; a control computer for sending a signal corresponding to the requests from terminals when send requests for the same signal at different times are received from a plurality of terminals under the condition of N>X, where N is the number of said signal sources, and X is the number of said memory circuit groups A, and for combining a plurality of memory circuit groups A to send the signal corresponding to the requests when the length of the signal of the signal source is longer than the memory capacity of a memory circuit group A; and, a switch group for serially connecting a number of said memory circuit groups A corresponding to the length of the source signal when a plurality of signal sources are requested from different terminal groups at the same time or at different times, and for connecting the electronic exchanger, signal sources, and of the unit memory circuit can be set at an arbitrary length!.

Claim 23

A signal distribution apparatus comprising: a signal source for generating a time serial signal whose contents change with time; a plurality of unit memory circuits U for storing a time length T of the output of said signal source; a delay means for delaying the signal by time TX by connecting X unit memory circuits U serially and transferring memory contents of each memory circuit to a successive memory circuit; a plurality of delayed signal read out means for reading out the memory contents of the unit memory circuit U when requested and maintaining synchronization with the transferring of the signal by said delay means; and, an electronic exchanger for outputting the signal from said delay signal read out means.

Claim 24

A signal distribution apparatus comprising: a signal source for generating a time serial signal whose contents change with time; a plurality of unit memory circuits U for storing a time length T of the output of said signal source; a delay means for delaying the signal by time TX by connecting X unit memory circuits U serially and transferring memory contents of each memory circuit to a successive memory circuit; a plurality of delayed signal read out means for reading out the memory contents of the unit memory circuit U when requested and maintaining synchronization with the transferring of the signal by said delay means; and, an electronic exchanger for outputting the signal from said delay signal read out means.