US5768306A
Expired / Lapsed
US
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Sliding correlator used in CDMA systems to establish initial synchronization
Assignee: NTT Docomo Inc
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Filing: 1997-07-25
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Granted: 1998-06-16
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Expires: 2017-07-25
Abstract
Abstract A sliding correlator is disclosed for establishing initial synchronization to spectrum-despread a received signal into a narrow band signal in a radio receiver in a spread spectrum CDMA system. The a sliding correlator can achieve high speed synchronization. A received signal is stored in a memory circuit (43). The received signal is read from the memory circuit (43) at a frequency substantially higher than the storing rate of the received signal. The read received signal is multiplied by a replica of a spreading code sequence by means of a multiplier (45), and the output signal of the multiplier (45) is accumulated by an accumulator (46) over a predetermined time period. The output of the accumulator (46) is decided by a threshold detector (47) whether or not it exceeds a predetermined threshold. When the output of the threshold detector (47) is less than the threshold, the phase of the spreading code sequence is shifted, and the detection is repeated. Since the correlation is taken by reading the received signal from the memory circuit (43) at a high speed, the initial synchronization can be established quickly.
Inventors
- 👤 Mamoru Sawahashi
- 👤 Fumiyuki Adachi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:35
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/7073; H04B1/7075; H04B1/709; H04B1/7095
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
183 words
A sliding correlator for a CDMA system using spreading code sequence with a chip rate of 1/TC where TC is a one chip period, comprising: a memory circuit for storing a received signal; a timing generator for generating a clock signal used for reading the received signal stored in said memory circuit at a frequency K times higher than a storing rate of (1/TC) of the received signal; a spreading code sequence replica generator for generating a replica of a spreading code sequence with a chip rate of K/TC; a multiplier for multiplying the read received signal with said replica of the spreading code sequence; an accumulator for accumulating an output signal of said multiplier over a predetermined time period; a threshold detector for detecting whether or not an output signal of said accumulator exceeds a predetermined threshold; and a clock generator for controlling said spreading code sequence replica generator to generate said spreading code sequence, said clock generator changing a phase of said replica of said spreading code sequence when a detection output of said threshold detector is less than the threshold.
Claim 2
Dependent Claim
183 words
A sliding correlator for a CDMA system using spreading code sequence with a chip rate of 1/TC where TC is a one chip period, comprising: a memory circuit for storing a received signal; a timing generator for generating a clock signal used for reading the received signal stored in said memory circuit at a frequency K times higher than a storing rate of (1/TC) of the received signal; a spreading code sequence replica generator for generating a replica of a spreading code sequence with a chip rate of K/TC; a multiplier for multiplying the read received signal with said replica of the spreading code sequence; an accumulator for accumulating an output signal of said multiplier over a predetermined time period; a threshold detector for detecting whether or not an output signal of said accumulator exceeds a predetermined threshold; and a clock generator for controlling said spreading code sequence replica generator to generate said spreading code sequence, said clock generator changing a phase of said replica of said spreading code sequence when a detection output of said threshold detector is less than the threshold.
Claim 3
Dependent Claim
228 words
A sliding correlator for CDMA systems using spreading code sequence with a chip rate of 1/TC where TC is one chip period, comprising: a memory circuit for storing a received signal; a timing generator for generating a clock signal used for reading the received signal stored in said memory circuit at a frequency K times higher than a storing rate of 1/TC of the received signal; a spreading code sequence replica generator for generating a plurality of replicas of a spreading code sequence with a chip rate of K/TC, said replicas having different phases; a plurality of multipliers, each of which multiplies the read received signal by one of said plurality of replicas of the spreading code sequence; a plurality of accumulators, each of which accumulates an output signal of one of said plurality of multipliers over a predetermined time period; a threshold detector for detecting whether or not each of output signals of said plurality of accumulators exceeds a predetermined threshold; and a clock generator for controlling said spreading code sequence replica generator to generate said spreading code sequence at the same rate as that of said clock signal (K/Tc), said clock generator changing the phases of said replicas of said spreading code sequence by using an output of said threshold detector when all output signals of said plurality of said accumulators are less than the threshold.
Claim 4
Dependent Claim
228 words
A sliding correlator for CDMA systems using spreading code sequence with a chip rate of 1/TC where TC is one chip period, comprising: a memory circuit for storing a received signal; a timing generator for generating a clock signal used for reading the received signal stored in said memory circuit at a frequency K times higher than a storing rate of 1/TC of the received signal; a spreading code sequence replica generator for generating a plurality of replicas of a spreading code sequence with a chip rate of K/TC, said replicas having different phases; a plurality of multipliers, each of which multiplies the read received signal by one of said plurality of replicas of the spreading code sequence; a plurality of accumulators, each of which accumulates an output signal of one of said plurality of multipliers over a predetermined time period; a threshold detector for detecting whether or not each of output signals of said plurality of accumulators exceeds a predetermined threshold; and a clock generator for controlling said spreading code sequence replica generator to generate said spreading code sequence at the same rate as that of said clock signal (K/Tc), said clock generator changing the phases of said replicas of said spreading code sequence by using an output of said threshold detector when all output signals of said plurality of said accumulators are less than the threshold.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-06-15 | 2001-12-15 | 2002-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-15 | 2005-12-15 | 2006-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-15 | 2009-12-15 | 2010-06-16 | $7700.00 | Window Closed / Lapsed |