Method and apparatus for adjusting phase-lock-loop parameters

Claim 3

The apparatus of claim 1, wherein said clock reference measure determines said measured transmission rate of clock reference values by measuring an arrival time between successive clock reference values in said bitstream.

Claim 4

The apparatus of claim 1, wherein said clock reference measure determines said measured transmission rate of clock reference values by computing a difference of successive clock reference values.

Claim 5

The apparatus of claim 1, wherein said PLL circuit comprises: a difference section, for computing a delta time between each of said clock reference values from said bitstream and a clock reference value in said PLL circuit; a first gain section, coupled to said difference section, for applying a gain factor "A" to said delta time; a second gain section, for applying a gain factor "1-A" to a delayed control signal; an adder, coupled to said first and second gain sections, for producing a control signal; a delay, coupled to said adder, for applying a delay to said control signal to produce said delayed control signal; and a voltage-controlled oscillator (VCO), coupled to said adder, responsive to said control signal for adjusting an output frequency.

Claim 6

The apparatus of claim 4, wherein said PLL circuit further comprises a counter, coupled to said VCO, responsive to said output frequency to maintain a clock reference value of said PLL circuit.

Claim 7

The apparatus of claim 5, wherein said gain factor "A" is selected at 0.25 and gain factor "1-A" is selected at 0.75 if said measured transmission rate of clock reference values is less than 0.7 seconds.

Claim 8

The apparatus of claim 6, wherein said gain factor "A" is selected at 0.0625 and gain factor "1-A" is selected at 0.9375 if said measured transmission rate of clock reference values is less than 0.1 seconds.

Claim 9

The apparatus of claim 7, wherein said counter is initialized if said measured transmission rate of clock reference values is less than 0 seconds.

Claim 10

The apparatus of claim 5, wherein said gain factor "A" is adjusted to produce a desired time constant in accordance with τ=N*ΔCR where τ is said desired time constant, ΔCR is said measured transmission rate of clock reference values and N is N=log (0.297)/log (1-A).

Claim 13

The method of claim 10, wherein said measuring step (a) comprises the step of measuring an arrival time between successive clock reference values in said bitstream.

Claim 14

The method of claim 10, wherein said measuring step (a) comprises the step of computing a difference from successive clock reference values.

Claim 15

The method of claim 10, wherein said determining step (b) comprises the step of applying said measured transmission rate of clock reference values to a plurality of predefined transmission rate levels.

Claim 16

The method of claim 10, wherein said gain parameter comprises a gain factor "A" and a gain factor "1-A".

Claim 17

The method of claim 14, wherein said adjusting step (c) comprises the step of changing the gain factors "A" and "1-A" in accordance with said measured transmission rate of clock reference values.

Claim 18

The method of claim 14, wherein said adjusting step (c) comprises the step of changing the gain factors "A" and "1-A" to modify a time constant in accordance with τ=N*ΔCR where τ is said desired time constant, ΔCR is said measured transmission rate of clock reference values and N is N=log (0.297)/log (1-A).