US5764172A
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Hybrid DAC suitable for use in a GPS receiver
Assignee: Trimble Inc
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Filing: 1996-04-05
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Granted: 1998-06-09
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Expires: 2016-04-05
Abstract
Abstract An apparatus including a hybrid digital-to-analog converter (DAC) (10) for converting a combined digital word (23) into a combined analog output level (21) and a GPS receiver (36) for providing the combined digital word (23) and using the combined analog output level (21) for phase locking a voltage controlled oscillator (VCO) (40) to a GPS satellite signal (34). The combined digital word (23) includes a more significant (MS) digital word (13) having N bits and a less significant (LS) digital word (15) having M bits. The hybrid DAC (10) includes a pulse generator DAC (12) for converting the MS digital word (13) into pulse output signal having a duty cycle and an average MS analog level representative of the MS digital word (13) and a second DAC (14) for converting the LS digital word (15) into an average LS analog level representative of the LS digital word (15). The pulse generator DAC (12) uses a counting technique in order to obtain a high degree of precision. A filter/combiner (18) filters and combines the average MS and the LS analog levels into a combined analog output level (21) representative of the combined digital word (21) to control the VCO (40) for providing a GPS-derived frequency signal (41) and a VCO signal to a correlator (38). The correlator (38) provides the combined digital word (23) representative of a difference between the frequency of the VCO signal and the frequency of the GPS satellite signal (34).
Inventors
- 👤 Eric B. Rodal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:04
CPC Classifications
G; G01; G01S; G01S19/00; G01S19/01; G01S19/13; G01S19/35; G01S19/37; H; H03; H03M; H03M1/00; H03M1/66; H03M1/68
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
150 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for filtering said MS pulse output signal for providing said average MS analog level and for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 2
Dependent Claim
150 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for filtering said MS pulse output signal for providing said average MS analog level and for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 3
Dependent Claim
154 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and for converting said LS digital word into an LS pulse output signal having said average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word, the filter/combiner including a filter for filtering said LS pulse output signal.
Claim 4
Dependent Claim
154 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and for converting said LS digital word into an LS pulse output signal having said average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word, the filter/combiner including a filter for filtering said LS pulse output signal.
Claim 5
Dependent Claim
162 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC including a binary summing DAC for receiving a less significant (LS) digital word having an LS digital level and for summing each successively more significant bit of said LS digital level with a weighting ratio of two to one more than the immediately less significant bit for converting said LS digital word to said average LS analog level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 6
Dependent Claim
162 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC including a binary summing DAC for receiving a less significant (LS) digital word having an LS digital level and for summing each successively more significant bit of said LS digital level with a weighting ratio of two to one more than the immediately less significant bit for converting said LS digital word to said average LS analog level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 7
Dependent Claim
186 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level including N bits and for converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level by receiving a clock signal, counting cycles of said clock signal, setting said MS pulse output signal when a cycle count of said clock signal reaches said MS digital level and resetting said MS pulse output signal and said cycle count when said cycle count reaches 2.sup.(N-1) ; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 8
Dependent Claim
186 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level including N bits and for converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level by receiving a clock signal, counting cycles of said clock signal, setting said MS pulse output signal when a cycle count of said clock signal reaches said MS digital level and resetting said MS pulse output signal and said cycle count when said cycle count reaches 2.sup.(N-1) ; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 9
Dependent Claim
166 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level including N bits and for converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level by receiving a clock signal, counting cycles of said clock signal, and issuing an MS pulse output signal at a rate proportional to said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 10
Dependent Claim
166 words
A hybrid digital-to-analog converter (DAC), comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level including N bits and for converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level by receiving a clock signal, counting cycles of said clock signal, and issuing an MS pulse output signal at a rate proportional to said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word.
Claim 11
Dependent Claim
31 words
The hybrid DAC of claim 1, wherein: said MS digital word includes N bits; said LS digital word includes M bits; and said N plus said M is at least sixteen.
Claim 12
Dependent Claim
99 words
The hybrid DAC of claim 1, wherein: said LS digital word includes M bits; and the filter/combiner includes a first resistor having a first node coupled to receive said MS pulse output signal and a second node coupled to a node of a capacitor; a second resistor having a first node coupled to receive said average LS analog level and a second node coupled to said node of said capacitor, said second resistor having a resistance of about 2 M times a resistance of said first resistor; and said node of said capacitor providing said combined analog output level.
Claim 13
Independent Claim
235 words
An apparatus for receiving a GPS satellite signal and providing a GPS-derived frequency signal, comprising: a hybrid digital-to-analog converter (DAC) comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC (14) for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word; and a GPS receiver, connected to the hybrid DAC, including a GPS antenna for receiving a GPS satellite signal from a GPS satellite, a voltage controlled oscillator (VCO) for using said combined analog output level for controlling a frequency of a GPS-derived frequency signal, and a correlator for providing said combined digital word representative of a frequency error between said GPS satellite signal and said GPS-derived frequency signal (41), whereby the frequency of said GPS-derived frequency signal is stabilized by said GPS satellite signal.
Claim 14
Independent Claim
235 words
An apparatus for receiving a GPS satellite signal and providing a GPS-derived frequency signal, comprising: a hybrid digital-to-analog converter (DAC) comprising: a pulse generator DAC for receiving a more significant (MS) digital word having an MS digital level and converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; a second DAC for receiving a less significant (LS) digital word having an LS digital level and converting said LS digital word into an average LS analog level representative of said LS digital level; and a filter/combiner coupled to the pulse generator DAC and the second DAC (14) for combining said average MS analog level and said average LS analog level for providing a combined analog output level representative of a combined digital level of a combined digital word including said MS digital word and said LS digital word; and a GPS receiver, connected to the hybrid DAC, including a GPS antenna for receiving a GPS satellite signal from a GPS satellite, a voltage controlled oscillator (VCO) for using said combined analog output level for controlling a frequency of a GPS-derived frequency signal, and a correlator for providing said combined digital word representative of a frequency error between said GPS satellite signal and said GPS-derived frequency signal (41), whereby the frequency of said GPS-derived frequency signal is stabilized by said GPS satellite signal.
Claim 15
Dependent Claim
24 words
The apparatus of claim 8, wherein: the filter/combiner is further for filtering said MS pulse output signal for providing said average MS analog level.
Claim 16
Dependent Claim
41 words
The apparatus of claim 8, wherein: the second DAC is for converting said LS digital word into an LS pulse output signal having said average LS analog level; and the filter/combiner includes a filter for filtering said LS pulse output signal.
Claim 17
Dependent Claim
53 words
The apparatus of claim 8, wherein: the second DAC includes a binary summing DAC for summing each successively more significant bit of said LS digital level with a weighting ratio of two to one more than the immediately less significant bit for converting said LS digital word to said average LS analog level.
Claim 18
Dependent Claim
66 words
The apparatus of claim 8, wherein: said MS digital word includes N bits; and the pulse generator DAC is for receiving a clock signal, counting cycles of said clock signal, setting said MS pulse output signal when a cycle count of said clock signal reaches said MS digital level and resetting said MS pulse output signal and said cycle count when said cycle count reaches 2.sup.(N-1).
Claim 19
Dependent Claim
46 words
The apparatus of claim 8, wherein: said MS digital word includes N bits; and the pulse generator DAC is for receiving a clock signal, counting cycles of said clock signal, and issuing an MS pulse output signal a at rate proportional to said MS digital level.
Claim 20
Dependent Claim
30 words
The apparatus of claim 8, wherein: said MS digital word includes N bits; said LS digital word includes M bits; and said N plus said M is at least sixteen.
Claim 21
Dependent Claim
98 words
The apparatus of claim 8, wherein: said LS digital word includes M bits; and the filter/combiner includes a first resistor having a first node coupled to receive said MS pulse output signal and a second node coupled to a node of a capacitor; a second resistor having a first node coupled to receive said average LS analog level and a second node coupled to said node of said capacitor, said second resistor having a resistance of about 2 M times a resistance of said first resistor; and said node of said capacitor providing said combined analog output level.
Claim 22
Independent Claim
159 words
A method in a hybrid digital-to-analog converter (DAC) for converting a combined digital word into a combined analog output level, comprising steps of: splitting said combined digital word into a more significant (MS) digital word having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; converting said LS digital word into an average LS analog level representative of said LS digital level by summing each successively more significant bit of said LS digital level with a weighting ratio of two to one greater than the immediately less significant bit; and combining said average MS analog level and said average LS analog level for providing said combined analog output level.
Claim 23
Independent Claim
159 words
A method in a hybrid digital-to-analog converter (DAC) for converting a combined digital word into a combined analog output level, comprising steps of: splitting said combined digital word into a more significant (MS) digital word having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; converting said LS digital word into an average LS analog level representative of said LS digital level by summing each successively more significant bit of said LS digital level with a weighting ratio of two to one greater than the immediately less significant bit; and combining said average MS analog level and said average LS analog level for providing said combined analog output level.
Claim 24
Independent Claim
180 words
A method in a hybrid digital-to-analog converter (DAC) for converting a combined digital word into a combined analog output level, comprising steps of: splitting said combined digital word into a more significant (MS) digital word including N bits having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level by steps of counting cycles of a clock signal; setting said MS pulse output signal when a cycle count of said clock signal reaches said MS digital level; and resetting said MS pulse output signal and said cycle count when said cycle count reaches 2.sup.(N-1) ; converting said LS digital word into an average LS analog level representative of said LS digital level; combining said average MS analog level and said average LS analog level for providing said combined analog output level.
Claim 25
Independent Claim
180 words
A method in a hybrid digital-to-analog converter (DAC) for converting a combined digital word into a combined analog output level, comprising steps of: splitting said combined digital word into a more significant (MS) digital word including N bits having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level by steps of counting cycles of a clock signal; setting said MS pulse output signal when a cycle count of said clock signal reaches said MS digital level; and resetting said MS pulse output signal and said cycle count when said cycle count reaches 2.sup.(N-1) ; converting said LS digital word into an average LS analog level representative of said LS digital level; combining said average MS analog level and said average LS analog level for providing said combined analog output level.
Claim 26
Dependent Claim
46 words
The method of claim 16, wherein: said MS digital word includes N bits; and the step of converting said MS digital word includes steps of counting cycles of a clock signal; issuing an MS pulse output signal at a rate proportional to said MS digital level.
Claim 27
Dependent Claim
30 words
The method of claim 16, wherein: said MS digital word includes N bits; said LS digital word includes M bits; and said N plus said M is at least sixteen.
Claim 28
Independent Claim
189 words
A method in a hybrid digital-to-analog converter (DAC) for converting a combined digital word into a combined analog output level, comprising steps of: splitting said combined digital word into a more significant (MS) digital word having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word including M bits having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; converting said LS digital word into an average LS analog level representative of said LS digital level; and combining said average MS analog level and said average LS analog level by steps of coupling said average MS analog level through a first resistor to a node of a capacitor; coupling said average LS analog level through a second resistor to said node of said capacitor, said second resistor having a resistance of 2 M times a resistance; and providing said combined analog output level (21) from said node of said capacitor.
Claim 29
Independent Claim
189 words
A method in a hybrid digital-to-analog converter (DAC) for converting a combined digital word into a combined analog output level, comprising steps of: splitting said combined digital word into a more significant (MS) digital word having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word including M bits having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; converting said LS digital word into an average LS analog level representative of said LS digital level; and combining said average MS analog level and said average LS analog level by steps of coupling said average MS analog level through a first resistor to a node of a capacitor; coupling said average LS analog level through a second resistor to said node of said capacitor, said second resistor having a resistance of 2 M times a resistance; and providing said combined analog output level (21) from said node of said capacitor.
Claim 30
Dependent Claim
23 words
The method of claim 17, further including a step of: filtering said MS pulse output signal for providing said average MS analog level.
Claim 31
Dependent Claim
34 words
The method of claim 17, further including steps of: converting said LS digital word into an LS pulse output signal; and filtering said LS pulse output signal for providing said average LS analog level.
Claim 32
Independent Claim
178 words
A method for providing a GPS-derived frequency signal, comprising steps of: receiving a GPS satellite signal from a GPS satellite; correlating said GPS satellite signal and said GPS-derived frequency signal for providing a combined digital word representative of a frequency error between said GPS satellite signal and said GPS-derived frequency signal, said combined digital word including a more significant (MS) digital word having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; converting said LS digital word into an average LS analog level representative of said LS digital level; combining said average MS analog level and said average LS analog level for providing said combined analog output level representative of said combined digital word; controlling a frequency of said GPS-derived frequency signal with said combined analog output level.
Claim 33
Independent Claim
178 words
A method for providing a GPS-derived frequency signal, comprising steps of: receiving a GPS satellite signal from a GPS satellite; correlating said GPS satellite signal and said GPS-derived frequency signal for providing a combined digital word representative of a frequency error between said GPS satellite signal and said GPS-derived frequency signal, said combined digital word including a more significant (MS) digital word having an MS digital level for the more significant bits of said combined digital word and a less significant (LS) digital word having an LS digital level for the less significant bits of said combined digital word; converting said MS digital word into an MS pulse output signal having an average MS analog level representative of said MS digital level; converting said LS digital word into an average LS analog level representative of said LS digital level; combining said average MS analog level and said average LS analog level for providing said combined analog output level representative of said combined digital word; controlling a frequency of said GPS-derived frequency signal with said combined analog output level.
Claim 34
Dependent Claim
23 words
The method of claim 23, further including a step of: filtering said MS pulse output signal for providing said average MS analog level.
Claim 35
Dependent Claim
34 words
The method of claim 23, further including steps of: converting said LS digital word into an LS pulse output signal; and filtering said LS pulse output signal for providing said average LS analog level.
Claim 36
Dependent Claim
41 words
The method of claim 23, wherein: the step of converting said LS digital word includes summing each successively more significant bit of said LS digital level with a weighting ratio of two to one greater than the immediately less significant bit.
Claim 37
Dependent Claim
67 words
The method of claim 23, wherein: said MS digital word includes N bits; and the step of converting said MS digital word includes steps of counting cycles of a clock signal; setting said MS pulse output signal when a cycle count of said clock signal reaches said MS digital level; and resetting said MS pulse output signal and said cycle count when said cycle count reaches 2.sup.(N-1).
Claim 38
Dependent Claim
47 words
The method of claim 23, wherein: said MS digital word includes N bits; and the step of converting said MS digital word includes steps of counting cycles of a clock signal; and issuing an MS pulse output signal at a rate proportional to said MS digital level.
References Cited (Backward Citations)
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Cited
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