Pulse width modulator (PWM) system with low cost dead time distortion correction

Claim 3

The system of claim 1, wherein the predetermined relation is that the load voltage is greater than the first predetermined value and current in the inductive load is of a first polarity.

Claim 4

The system of claim 1, wherein the first time occurs at an edge of the first PWM signal.

Claim 5

The system of claim 1, wherein the voltage sensor further produces the first value of the output signal when the load voltage is in a predetermined relation to a second predetermined value.

Claim 6

The system of claim 1, wherein the system is formed as an integrated circuit.

Claim 7

The system of claim 1, wherein the voltage sensor is a hysteresis device.

Claim 8

A near-zero current detection circuit for distortion correction of an inductive load powered by a pair of transistors controlled by a first modulated signal and a second modulated signal, wherein a dead-time occurs between the first modulated signal and the second modulated signal during which neither modulated signal is asserted, comprising: a voltage sensor connected to the inductive load, the voltage sensor sensing a load voltage of the inductive load and producing a first value of an output signal when the load voltage is in a predetermined relation to a first predetermined value; a first latch receiving the output signal from the voltage sensor at an input to the first latch, the first latch being controlled by the first modulated signal; and a second latch receiving the output signal from the voltage sensor at an input to the second latch, the second latch being controlled by the second modulated signal; wherein a different value for the latched output signal of the first latch and the latched output signal of the second latch indicates that output current of the inductive load is within a predetermined magnitude of zero.

Claim 9

A near-zero current detection circuit for distortion correction of an inductive load powered by a pair of transistors controlled by a first modulated signal and a second modulated signal, wherein a dead-time occurs between the first modulated signal and the second modulated signal during which neither modulated signal is asserted, comprising: a voltage sensor connected to the inductive load, the voltage sensor sensing a load voltage of the inductive load and producing a first value of an output signal when the load voltage is in a predetermined relation to a first predetermined value; a first latch receiving the output signal from the voltage sensor at an input to the first latch, the first latch being controlled by the first modulated signal; and a second latch receiving the output signal from the voltage sensor at an input to the second latch, the second latch being controlled by the second modulated signal; wherein a different value for the latched output signal of the first latch and the latched output signal of the second latch indicates that output current of the inductive load is within a predetermined magnitude of zero.

Claim 10

The circuit of claim 7, wherein the predetermined relation is that the load voltage is greater than the first predetermined value and current in the inductive load is of a first polarity.

Claim 11

The circuit of claim 7, wherein the voltage sensor further produces the first value of the output signal when the load voltage is in a predetermined relation to a second predetermined value.

Claim 12

The circuit of claim 7, wherein the first latch is controlled by the first modulated signal such that the output signal is latched by an edge of the first modulated signal

Claim 13

The circuit of claim 7, wherein the circuit is formed as an integrated circuit.

Claim 14

The circuit of claim 7, wherein the voltage sensor is a hysteresis device.

Claim 15

The circuit of claim 7, further comprising a pulse-width modulator that receives the output signal latched by the first latch and the output signal latched by the second latch and generates the first modulated signal and the second modulated signal, the pulse-width modulator being adapted to correct for distortion in the output current of the inductive load induced by commutation of the output current during dead-time by modifying a duty-cycle of one of the first and second modulated signals and, upon the occurance of a different value being output from the first latch than is output from the second latch, modifying a duty-cycle of the other of the first and second modulated signals, the other of the first and second modulated signals being modified prior to the output current being equal to zero to correct for near-zero distortion.

Claim 16

A data processing system for driving an inductive load powered by a pair of transistors controlled by a first pulse-width-modulated (PWM) signal and a second PWM signal, comprising: a voltage sensor connected to the inductive load, the voltage sensor sensing a load voltage of the inductive load and producing a first value of an output signal when the load voltage is in a first state relative to a predetermined value; a first latch receiving the output signal from the voltage sensor at an input to the first latch, the first latch being controlled by the first PWM signal such that the output signal is latched by an edge of the first PWM signal and output as a first latched output signal; a second latch receiving the output signal from the voltage sensor at an input to the second latch, the second latch being controlled by the second PWM signal such that the output signal is latched by an edge of the second PWM signal and output as a second latched output signal; a processor that receives the first latched output signal and the second latched output signal and generates the first PWM signal and the second PWM signal, wherein a dead-time is placed between the first PWM signal and the second PWM signal during which neither PWM signal is asserted, and wherein the processor modifies a duty-cycle of one of the first and second PWM signals and, upon the occurance of the first latched output signal being different than the second latched output signal, the processor modifies a duty-cycle of the other of the first and second PWM signals to correct for distortion in the output current of the inductive load induced by commutation of the output current during dead-time, the other of the first and second PWM signals being modified prior to the output current being equal to zero to correct for near-zero distortion of the output current.

Claim 17

A data processing system for driving an inductive load powered by a pair of transistors controlled by a first pulse-width-modulated (PWM) signal and a second PWM signal, comprising: a voltage sensor connected to the inductive load, the voltage sensor sensing a load voltage of the inductive load and producing a first value of an output signal when the load voltage is in a first state relative to a predetermined value; a first latch receiving the output signal from the voltage sensor at an input to the first latch, the first latch being controlled by the first PWM signal such that the output signal is latched by an edge of the first PWM signal and output as a first latched output signal; a second latch receiving the output signal from the voltage sensor at an input to the second latch, the second latch being controlled by the second PWM signal such that the output signal is latched by an edge of the second PWM signal and output as a second latched output signal; a processor that receives the first latched output signal and the second latched output signal and generates the first PWM signal and the second PWM signal, wherein a dead-time is placed between the first PWM signal and the second PWM signal during which neither PWM signal is asserted, and wherein the processor modifies a duty-cycle of one of the first and second PWM signals and, upon the occurance of the first latched output signal being different than the second latched output signal, the processor modifies a duty-cycle of the other of the first and second PWM signals to correct for distortion in the output current of the inductive load induced by commutation of the output current during dead-time, the other of the first and second PWM signals being modified prior to the output current being equal to zero to correct for near-zero distortion of the output current.

Claim 18

A microcontroller for current distortion correction of an inductive load powered by a pair of transistors controlled by a first modulated signal and a second modulated signal, wherein a deadtime occurs between the first modulated signal and the second modulated signal during which neither modulated signal is asserted, comprising: a device that senses a load voltage of the inductive load; a latching device that stores a first value indicating the level of the load voltage during a first dead-time and stores a second value indicating the level of the load voltage during a second deadtime; and a controller that receives the stored values in the latching device and generates signals for correcting current distortion in response to the first value and the second value indicating selected levels.

Claim 19

A microcontroller for current distortion correction of an inductive load powered by a pair of transistors controlled by a first modulated signal and a second modulated signal, wherein a deadtime occurs between the first modulated signal and the second modulated signal during which neither modulated signal is asserted, comprising: a device that senses a load voltage of the inductive load; a latching device that stores a first value indicating the level of the load voltage during a first dead-time and stores a second value indicating the level of the load voltage during a second deadtime; and a controller that receives the stored values in the latching device and generates signals for correcting current distortion in response to the first value and the second value indicating selected levels.

Claim 20

The microcontroller of claim 15, wherein the first and second modulated signals are pulse-width-modulated signals.

Claim 21

The microcontroller of claim 15, wherein the latching device is a hysteresis device.

Claim 22

The microcontroller of claim 15, wherein the microcontroller is formed as an integrated circuit.

Claim 23

The microcontroller of claim 15, further comprising a modulator that generates the first modulated signal and the second modulated signal and modifies the first and second modulated signals in response to the signals generated by the controller, the first modulated signal being modified prior to output current of the inductive load being equal to zero to correct for near-zero distortion.

Claim 26

The method according to claim 20, wherein the selected levels are when the first load voltage is different than the second load voltage, indicating that output current of the inductive load is within a predetermined magnitude of zero.

Claim 27

The method according to claim 20, wherein the selected levels are when the first load voltage is greater than a predetermined value and current in the inductive load is of a first polarity.

Claim 28

The method according to claim 20, further comprising the step of generating the first PWM signal and the second PWM signal.

Claim 29

The method according to claim 20, further comprising the step of modifying the first and second PWM signals in response to the generated signals, the first PWM signal being modified prior to output current of the inductive load being equal to zero to correct for near-zero distortion.

Claim 30

A data processing system comprising: a central processing unit having an output terminal connected to an address bus, and a bidirectional connection to a data bus; a memory having an input terminal coupled to said address bus, and an output terminal coupled to said data bus, said memory including a plurality of storage locations which store a corresponding plurality of instructions which control the data processing system; a pulse width modulator having a first input terminal coupled to said address bus, a second input terminal coupled to said data bus, and an output terminal for providing at least first and second control signals; said first and second control signals adapted to be coupled to an inverter which drives an input of a motor; and a low current condition circuit having an input terminal adapted to receive a voltage signal which indicates a voltage at the input of the motor, and having an address input terminal coupled to said address bus, and a data output terminal coupled to said data bus for providing a low current condition signal in response to said voltage signal.

Claim 31

A data processing system comprising: a central processing unit having an output terminal connected to an address bus, and a bidirectional connection to a data bus; a memory having an input terminal coupled to said address bus, and an output terminal coupled to said data bus, said memory including a plurality of storage locations which store a corresponding plurality of instructions which control the data processing system; a pulse width modulator having a first input terminal coupled to said address bus, a second input terminal coupled to said data bus, and an output terminal for providing at least first and second control signals; said first and second control signals adapted to be coupled to an inverter which drives an input of a motor; and a low current condition circuit having an input terminal adapted to receive a voltage signal which indicates a voltage at the input of the motor, and having an address input terminal coupled to said address bus, and a data output terminal coupled to said data bus for providing a low current condition signal in response to said voltage signal.

Claim 32

The data processing system of claim 25 wherein said voltage signal comprises a logic signal which indicates whether said voltage at the input of the motor is within a predetermined range of a zero level.

Claim 33

The data processing system of claim 26 wherein said low current condition circuit provides said low current condition signal when said logic signal is in a first logic state at a first predetermined point in time and said logic signal is in a second logic state at a second predetermined point in time.

Claim 34

The data processing system of claim 27 wherein said first predetermined point in time is an end of a dead time interval during a first cycle of said pulse width modulator, and said second predetermined point in time is an end of said dead time interval during a second cycle immediately subsequent to said first cycle.

Claim 35

The data processing system of claim 25 further comprising a voltage sensor having an input terminal adapted to be coupled to the motor, and an output terminal for providing said voltage signal.

Claim 36

The data processing system of claim 29 wherein said central processing unit, said memory, said pulse width modulator, said low current condition circuit, and said voltage sensor are all implemented on a single integrated circuit.

Claim 37

The data processing system of claim 29 wherein said voltage signal is provided by a circuit element comprising one of a group consisting of a voltage sensor, an analog-to-digital converter (ADC), a Schmitt trigger, a comparator which has hysteresis, a comparator having at least two switchable threshold voltages, and a transition detector circuit.

Claim 38

The data processing system of claim 25 wherein said central processing unit, said memory, said pulse width modulator, and said low current condition circuit are all implemented on a single integrated circuit.

Claim 39

The data processing system of claim 25 wherein said low current condition circuit comprises: a first flip-flop having a data input terminal for receiving said voltage signal, a clock input terminal for receiving a first clock signal, and an output terminal; a second flip-flop having a data input terminal for receiving said voltage signal, a clock input terminal for receiving a second clock signal, and an output terminal; and a register having a first input terminal coupled to said output terminal of said first flip-flop, a second input terminal coupled to said output terminal of said second flip-flop, an address input terminal coupled to said address bus, and an output terminal coupled to said data bus.

Claim 40

The data processing system of claim 33 wherein said first clock signal is said first control signal of said pulse width modulator, and wherein said second clock signal is said second control signal of said pulse width modulator.

Claim 41

The data processing system of claim 25 wherein said low current condition circuit detects a low current condition by providing a predetermined output signal to said data output terminal thereof.

Claim 42

The data processing system of claim 35 wherein said central processing unit periodically reads a value at said data output terminal of said low current condition circuit and in response to said predetermined output signal, said central processing unit programs said pulse width modulator to change an operating characteristic thereof.

Claim 43

The data processing system of claim 36 wherein said operating characteristic comprises a duty cycle of said first and second control signals.