US5760602A
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Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
Assignee: Miralfin SRL
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Filing: 1996-01-17
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Granted: 1998-06-02
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Expires: 2016-01-17
Abstract
Abstract A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.
Inventors
- 👤 Charles M. C. Tan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17752; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; H03K19/1733; H03K19/1737; H03K19/17704; H03K19/17756; H03K19/1776
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
172 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of the memory cells comprises a half static random access memory cell and the time slice selector comprises a plurality of P-channel transistors wherein a P-channel transistor corresponds with each of the plurality of half static random access memory cells and wherein a half static random access memory cell determines the setting of a corresponding programmable switch element when the corresponding P-channel transistor is turned on; and wherein the time slice selector comprises a shift register.
Claim 2
Dependent Claim
172 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of the memory cells comprises a half static random access memory cell and the time slice selector comprises a plurality of P-channel transistors wherein a P-channel transistor corresponds with each of the plurality of half static random access memory cells and wherein a half static random access memory cell determines the setting of a corresponding programmable switch element when the corresponding P-channel transistor is turned on; and wherein the time slice selector comprises a shift register.
Claim 3
Dependent Claim
112 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element: a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a pipeline synchronizer allows the settings of the programmable switch element to be synchronized to a synchronization clock.
Claim 4
Dependent Claim
112 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element: a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a pipeline synchronizer allows the settings of the programmable switch element to be synchronized to a synchronization clock.
Claim 5
Dependent Claim
132 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of switch elements determine the configuration of a voice recognition template and a plurality of digital voice recognition templates are stored in the plurality of memory cells corresponding with each of the plurality of switch elements.
Claim 6
Dependent Claim
132 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of switch elements determine the configuration of a voice recognition template and a plurality of digital voice recognition templates are stored in the plurality of memory cells corresponding with each of the plurality of switch elements.
Claim 7
Dependent Claim
132 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of switch elements determine the configuration of an image recognition template and a plurality of digital image recognition templates are stored in the plurality of memory cells corresponding with each of the plurality of switch elements.
Claim 8
Dependent Claim
132 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of switch elements determine the configuration of an image recognition template and a plurality of digital image recognition templates are stored in the plurality of memory cells corresponding with each of the plurality of switch elements.
Claim 9
Dependent Claim
181 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of the memory cells comprises a half static random access memory cell and the time slice selector comprises a plurality of P-channel transistors wherein a P-channel transistor corresponds with each of the plurality of half static random access memory cells and wherein a half static random access memory cell determines the setting of a corresponding programmable switch element when the corresponding P-channel transistor is turned on; and wherein a level shifter ensures that the programmable switch element is fully set to one of two states.
Claim 10
Dependent Claim
181 words
A memory system for time multiplexing between a plurality of settings of a programmable switch element within a FPGA, the system comprising: a plurality of memory cells storing predetermined settings of the programmable switch element; a time slice selector receiving an output from each of the plurality of memory cells and selecting one of the outputs from the memory cells to drive the programmable switch element; and a time slice controller controlling the time slice selector and determining which of the plurality of memory cells is selected to drive the programmable switch element; wherein a plurality of the memory cells comprises a half static random access memory cell and the time slice selector comprises a plurality of P-channel transistors wherein a P-channel transistor corresponds with each of the plurality of half static random access memory cells and wherein a half static random access memory cell determines the setting of a corresponding programmable switch element when the corresponding P-channel transistor is turned on; and wherein a level shifter ensures that the programmable switch element is fully set to one of two states.
Claim 11
Dependent Claim
18 words
The memory system as recited in claim 5, wherein the programmable switch element is a look-up table input.
Claim 12
Dependent Claim
18 words
The memory system as recited in claim 5, wherein the programmable switch element is a multiplexer control input.
Claim 13
Dependent Claim
32 words
The memory system as recited in claim 5, wherein the time slice controller is connected to a user provided clock which clocks the time slice controller through a predetermined number of states.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |