US5754489A
Expired / Lapsed
US
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Serial access memory apparatus
Assignee: Chiao Tung Holdings LLC
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Filing: 1996-12-13
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Granted: 1998-05-19
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Expires: 2016-12-13
Abstract
Abstract An improved serial access memory apparatus which is capable of more stably and rapidly processing a data transmission between a memory cell array and a serial access memory or between serial access memories, which includes a first power controller for generating a first power control signal having different levels and for applying it to a first serial access memory in accordance with a first write enable signal outputted from a read/write controller for controlling a read/write operation of a memory cell array, and a second power controller for generating a second power control signal having different levels and for applying it to a second serial access memory in accordance with a second write enable signal outputted from the read/write controller.
Inventors
- 👤 Young Ho Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:44
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G06; G06F; G06F12/00; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
279 words
A serial access memory apparatus having first and second serial access memories, and a memory cell array, comprising: a read/write controller for controlling a read/write operation of the memory cell array by outputting first and second write enable signals; a first power controller for receiving the first write enable signal having one of a first and a second level and applying a first power control signal to the first serial access memory; and a second power controller for receiving the first write enable signal having the other one of a first and second levels and applying a second power control signal to the second serial access memory, wherein said first power controller includes: a rising edge detector for detecting the rising edge of the first write enable signal; a delay unit for delaying the first write enable signal: an inverter for inverting the output Signal of the delay unit; a NOR gate fox NORing the output signal of the inverter and the output signal of the rising edge detector; a first NMOS transistor having a gate for receiving the output signal of the rising edge detector and a source for receiving a low level voltage; a PMOS transistor having a gate for receiving the first write enable signal a source for receiving a high level voltage and a drain connected to a drain of the NMOS transistor; and a second NMOS transistor having a gate for receiving the output signal of the NOR gate a drain for receiving the high level voltage, and a source commonly connected to the drain of the first NMOS transistor and the drain of the EMOS transistor for outputting the first power control signal.
Claim 2
Dependent Claim
279 words
A serial access memory apparatus having first and second serial access memories, and a memory cell array, comprising: a read/write controller for controlling a read/write operation of the memory cell array by outputting first and second write enable signals; a first power controller for receiving the first write enable signal having one of a first and a second level and applying a first power control signal to the first serial access memory; and a second power controller for receiving the first write enable signal having the other one of a first and second levels and applying a second power control signal to the second serial access memory, wherein said first power controller includes: a rising edge detector for detecting the rising edge of the first write enable signal; a delay unit for delaying the first write enable signal: an inverter for inverting the output Signal of the delay unit; a NOR gate fox NORing the output signal of the inverter and the output signal of the rising edge detector; a first NMOS transistor having a gate for receiving the output signal of the rising edge detector and a source for receiving a low level voltage; a PMOS transistor having a gate for receiving the first write enable signal a source for receiving a high level voltage and a drain connected to a drain of the NMOS transistor; and a second NMOS transistor having a gate for receiving the output signal of the NOR gate a drain for receiving the high level voltage, and a source commonly connected to the drain of the first NMOS transistor and the drain of the EMOS transistor for outputting the first power control signal.
Claim 3
Dependent Claim
40 words
The apparatus of claim 1, wherein said first and second power controllers output the first and second power control signals at predetermined levels different from each other when serial data is transmitted between the first and second serial access memories.
Claim 4
Dependent Claim
43 words
The apparatus of claim 1, wherein said first power controller outputs the first power control signal having a predetermined level higher than the second power control signal outputted from the second power controller when serial data is read from the memory cell array.
Claim 5
Dependent Claim
43 words
The apparatus of claim 1, wherein said first power controller outputs the first power control signal having a predetermined level lower than the second power control signal outputted from the second power controller when serial data is written in the memory cell array.
Claim 6
Dependent Claim
64 words
The apparatus of claim 1, wherein said rising edge detector includes: a delay unit for delaying the first write enable signal; a first inverter for inverting the output signal of the delay unit; a NAND gate for NANDing the output signal of the first inverter and the first write enable signal; and a second inverter for inverting the output signal of the NAND gate.
Claim 7
Dependent Claim
274 words
A serial access memory apparatus having first and second serial access memories and a memory cell array comprising; read/write controller for controlling read/write operation of the memory cell array by outputting first and second write enable signals: a first power controller for receiving the first write enable signal having one of a first and a second level and applying a first power control signal to the first serial access memory; and a second power controller for receiving the first write enable signal having the other one of the first and second levels and applying a second power control signal to the second serial access memory. wherein said second power controller includes: a rising edge detector for detecting a rising edge of the second write enable signal; a delay unit for delaying the second write enable signal; an inverter for inverting the output signal of the delay unit; a NOR gate for NORing the output signal of the inverter and the output signal of the rising edge detector, a first NMOS transistor having a gate for receiving the output signal of the rising edge detector and a source for receiving a low level voltage; a PMOS transistor having a gate for receiving the second write enable signal, a source for receiving a high level voltage, and a drain connect of the NMOS transistor, and a second NMOS transistor having a gate for receiving the output signal of the NOR gate, a drain for receiving the high level voltage, and a source commonly connected to the drain of the first NMOS transistor and the drain of the PMOS transistor for outputting the second power control signal.
Claim 8
Dependent Claim
274 words
A serial access memory apparatus having first and second serial access memories and a memory cell array comprising; read/write controller for controlling read/write operation of the memory cell array by outputting first and second write enable signals: a first power controller for receiving the first write enable signal having one of a first and a second level and applying a first power control signal to the first serial access memory; and a second power controller for receiving the first write enable signal having the other one of the first and second levels and applying a second power control signal to the second serial access memory. wherein said second power controller includes: a rising edge detector for detecting a rising edge of the second write enable signal; a delay unit for delaying the second write enable signal; an inverter for inverting the output signal of the delay unit; a NOR gate for NORing the output signal of the inverter and the output signal of the rising edge detector, a first NMOS transistor having a gate for receiving the output signal of the rising edge detector and a source for receiving a low level voltage; a PMOS transistor having a gate for receiving the second write enable signal, a source for receiving a high level voltage, and a drain connect of the NMOS transistor, and a second NMOS transistor having a gate for receiving the output signal of the NOR gate, a drain for receiving the high level voltage, and a source commonly connected to the drain of the first NMOS transistor and the drain of the PMOS transistor for outputting the second power control signal.
Claim 9
Dependent Claim
64 words
The apparatus of claim 6, wherein said rising edge detector includes: a delay unit for delaying the second write enable signal; a first inverter for inverting the output signal of the delay unit; a NAND gate for NANDing the output signal of the first inverter and the second write enable signal; and a second inverter for inverting the output signal of the NAND gate.
Claim 10
Dependent Claim
39 words
The apparatus of claim 6, wherein said first and power controllers output the first and second power control signals at predetermined levels different from each other when serial data is transmitted between the first and second serial access memories.
Claim 11
Dependent Claim
43 words
The apparatus of claim 6, wherein said first power controller outputs the first power control signal having a predetermined level higher than the second power control signal outputted from the second power controller when serial data is read from the memory cell array.
Claim 12
Dependent Claim
43 words
The apparatus of claim 6, wherein said first power controller outputs the first power control signal having a predetermined level lower than the second power control signal outputted from the second power controller when serial data is written in the memory cell array.
References Cited (Backward Citations)
US5377154A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |