US5751628A
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Ferroelectric memory devices and method for testing them
Assignee: Pannova Semic LLC
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Filing: 1996-08-20
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Granted: 1998-05-12
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Expires: 2016-08-20
Abstract
Abstract A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.
Inventors
- 👤 Hiroshige Hirano
- 👤 Nobuyuki Moriwaki
- 👤 Tetsuji Nakakuma
- 👤 Toshiyuki Honda
- 👤 George Nakane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:25
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/10; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
215 words
A ferroelectric memory device comprising: first and second bit lines; a first ferroelectric capacitor connected to said first bit line through a first memory cell transistor, said first capacitor constituting a main memory cell; a second ferroelectric capacitor connected to said second bit line through a second memory cell transistor, said second capacitor constituting the main memory cell; a third ferroelectric capacitor connected to said second bit line through a third memory cell transistor, said third capacitor constituting a first reference memory cell; a fourth ferroelectric capacitor connected to said first bit line through a fourth memory cell transistor, said fourth capacitor constituting a second reference memory cell; a first word line connected to a gate of said first memory cell transistor; a second word line connected to a gate of said second memory cell transistor; a third word line connected to a gate of said third memory cell transistor; a fourth word line connected to a gate of said fourth memory cell transistor; and a control circuit for controlling said first to fourth word lines, said control circuit functioning to control first and second operation modes, by controlling either said first or second word line in said first operation mode, and controlling both said first and second word lines in said second operation mode.
Claim 2
Dependent Claim
215 words
A ferroelectric memory device comprising: first and second bit lines; a first ferroelectric capacitor connected to said first bit line through a first memory cell transistor, said first capacitor constituting a main memory cell; a second ferroelectric capacitor connected to said second bit line through a second memory cell transistor, said second capacitor constituting the main memory cell; a third ferroelectric capacitor connected to said second bit line through a third memory cell transistor, said third capacitor constituting a first reference memory cell; a fourth ferroelectric capacitor connected to said first bit line through a fourth memory cell transistor, said fourth capacitor constituting a second reference memory cell; a first word line connected to a gate of said first memory cell transistor; a second word line connected to a gate of said second memory cell transistor; a third word line connected to a gate of said third memory cell transistor; a fourth word line connected to a gate of said fourth memory cell transistor; and a control circuit for controlling said first to fourth word lines, said control circuit functioning to control first and second operation modes, by controlling either said first or second word line in said first operation mode, and controlling both said first and second word lines in said second operation mode.
Claim 3
Dependent Claim
20 words
The ferroelectric memory device according to claim 1, wherein said first and second memory cells are located adjacent each other.
Claim 4
Dependent Claim
32 words
The ferroelectric memory device according to claim 1, further comprising a voltage sensing circuit, wherein the first and second operation modes are controlled by an output signal from said voltage sensing circuit.
Claim 5
Dependent Claim
29 words
The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device tests itself in said second operation mode, and then tests itself in said first operation mode.
Claim 6
Dependent Claim
33 words
The ferroelectric memory device according to claim 4, wherein the ferroelectric memory device performs a writing operation in said second operation mode, and then, performs a reading operation in said first operation mode.
Claim 7
Dependent Claim
39 words
The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device tests itself in said second operation mode, and then, tests itself in said first operation mode if the test in said second operation mode is passed.
Claim 8
Dependent Claim
57 words
The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device writes data into the first ferroelectric capacitor in said first operation mode using a first supply voltage, and writes data into the second ferroelectric capacitor in said first operation mode using a second supply voltage, and then reads data in said second operation mode.
Claim 9
Dependent Claim
59 words
The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device writes H data into the first ferroelectric capacitor in said first operation mode using a first supply voltage, and writes H data into the second ferroelectric capacitor in said first operation mode using a second supply voltage, and then reads data in said second operation mode.
Claim 10
Dependent Claim
59 words
The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device writes L data into the first ferroelectric capacitor in said first operation mode using a first supply voltage, and writes L data into the second ferroelectric capacitor in said first operation mode using a second supply voltage, and then reads data in said second operation mode.
Claim 11
Dependent Claim
59 words
The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device writes H data into the first ferroelectric capacitor in said first operation mode using a first supply voltage, and writes L data into the second ferroelectric capacitor in said first operation mode using a second supply voltage, and then reads data in said second operation mode.
Claim 12
Independent Claim
142 words
A method for testing a ferroelectric memory device that comprises first and second bit lines, a first ferroelectric capacitor forming a main memory cell and connected to said first bit line through a first memory cell transistor, a second ferroelectric capacitor forming the main memory cell and connected to said second bit line through a second memory cell transistor, a first word line connected to a gate of said first memory cell transistor, a second word line connected to a gate of said second memory cell transistor, and a control circuit for controlling either said first or second word line in a first operation mode and controlling both said first and second word lines in a second operation mode, the method comprising the steps of testing the device in said first operation mode, and testing the device in said second operation mode.
Claim 13
Independent Claim
142 words
A method for testing a ferroelectric memory device that comprises first and second bit lines, a first ferroelectric capacitor forming a main memory cell and connected to said first bit line through a first memory cell transistor, a second ferroelectric capacitor forming the main memory cell and connected to said second bit line through a second memory cell transistor, a first word line connected to a gate of said first memory cell transistor, a second word line connected to a gate of said second memory cell transistor, and a control circuit for controlling either said first or second word line in a first operation mode and controlling both said first and second word lines in a second operation mode, the method comprising the steps of testing the device in said first operation mode, and testing the device in said second operation mode.
Claim 14
Dependent Claim
28 words
The method according to claim 11, wherein the step of testing in said second operation mode is performed before the step of testing in said first operation mode.
Claim 15
Dependent Claim
34 words
The method according to claim 12, wherein the step of testing in said second operation mode includes writing operation, and the step of testing of testing in said first operation mode includes reading operation.
Claim 16
Dependent Claim
30 words
The method according to claim 12, wherein the step of testing in said first operation mode is performed only when the test in said second operation mode has been passed.
Claim 17
Dependent Claim
28 words
The method according to claim 11, wherein the step of testing in said first operation mode is performed before the step of testing in said second operation mode.
Claim 18
Dependent Claim
55 words
The method according to claim 15, wherein the step of testing in said first operation mode includes writing data into the first ferroelectric capacitor using a first supply voltage and writing data into the second ferroelectric capacitor using a second supply voltage, and the step of testing in said second operation mode includes reading operation.
Claim 19
Dependent Claim
44 words
The method according to claim 16, wherein the step of testing in said first operation mode includes writing H data into the first ferroelectric capacitor using a first supply voltage and writing H data into the second ferroelectric capacitor using a second supply voltage.
Claim 20
Dependent Claim
44 words
The method according to claim 16, wherein the step of testing in said first operation mode includes writing L data into the first ferroelectric capacitor using a first supply voltage and writing L data into the second ferroelectric capacitor using a second supply voltage.
Claim 21
Dependent Claim
44 words
The method according to claim 16, wherein the step of testing in said first operation mode includes writing H data into the first ferroelectric capacitor using a first supply voltage and writing L data into the second ferroelectric capacitor using a second supply voltage.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |