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US5747994A Expired / Lapsed US ⏱️ 0.0 years remaining

Board exchange mechanism for semiconductor test system

Assignee: Advantest Corp
•
Filing: 1996-04-26
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Granted: 1998-05-05
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Expires: 2016-04-26
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Abstract

Abstract A board exchange mechanism for a self-diagnosis process excludes the need of disconnecting a test head from a wafer prober for installing a self-diagnosis board. The board exchange mechanism for a semiconductor test system having a plurality of test channels includes: a test head connected to the semiconductor test system and having a plurality of print circuit boards corresponding to the plurality of test channels; a wafer prober having a pin card for electrically contacting a semiconductor wafer to be tested for supplying test signals to the semiconductor wafer; a performance board for interfacing the plurality of print circuit boards and the pin card when the test head and the wafer prober are mechanically connected with each other; a self-diagnosis board which is sized equal to the size of the pin card of the wafer prober; wherein the pin card is replaced with the self-diagnosis board prior to a self-diagnosis test while the test head and the wafer prober remain mechanically connected and wherein the performance board interfaces the plurality of print circuit boards and the self-diagnosis board.

Inventors

  • 👤 Kazunari Suga

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 09:54
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/06705; H; H10; H10P; H10P74/00

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 184 words
A board exchange mechanism for a semiconductor test system having a plurality of test channels, said board exchange mechanisms is used for performing a self-diagnosis test, comprising: a test head connected to said semiconductor test system and having a plurality of print circuit boards corresponding to said plurality of test channels; a wafer prober having a pin card for electrically contacting a semiconductor wafer to be tested for supplying test signals from said semiconductor test system to said semiconductor wafer and transmitting output signals from said semiconductor wafer to said semiconductor test system; a performance board for interfacing said plurality of print circuit boards and said pin card when said test head and said wafer prober are mechanically connected with each other; a self-diagnosis board which is sized equal to the size of said pin card of said wafer prober; wherein said pin card is replaced with said self-diagnosis board prior to a self-diagnosis test while said test head and said wafer prober remain mechanically connected with each other, and said performance board interfacing said plurality of print circuit boards and said self-diagnosis board.
Claim 2
Dependent Claim 184 words
A board exchange mechanism for a semiconductor test system having a plurality of test channels, said board exchange mechanisms is used for performing a self-diagnosis test, comprising: a test head connected to said semiconductor test system and having a plurality of print circuit boards corresponding to said plurality of test channels; a wafer prober having a pin card for electrically contacting a semiconductor wafer to be tested for supplying test signals from said semiconductor test system to said semiconductor wafer and transmitting output signals from said semiconductor wafer to said semiconductor test system; a performance board for interfacing said plurality of print circuit boards and said pin card when said test head and said wafer prober are mechanically connected with each other; a self-diagnosis board which is sized equal to the size of said pin card of said wafer prober; wherein said pin card is replaced with said self-diagnosis board prior to a self-diagnosis test while said test head and said wafer prober remain mechanically connected with each other, and said performance board interfacing said plurality of print circuit boards and said self-diagnosis board.

References Cited (Backward Citations)

US3665504A Cited
US3599092A Cited
US4918374A Cited
US5489843A Cited
US5448164A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-05-04 2001-11-03 2002-05-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-05-04 2005-11-03 2006-05-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-05-04 2009-11-03 2010-05-05 $7700.00 Window Closed / Lapsed

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