US5747831A
Expired / Lapsed
US
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SIC field-effect transistor array with ring type trenches and method of producing them
Assignee: Wolfspeed Inc
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Filing: 1995-06-27
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Granted: 1998-05-05
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Expires: 2015-06-27
Abstract
Abstract SiC field-effect transistors with source, gate and drain contacts and in which the source contacts are located on the surface of the semiconductor wafer, the drain contacts on the underside of the wafer and the gate contacts in trench-like structures. The trench-like structures surround the source electrodes of the transistors in the shape of a ring and the gate contacts are connected to each other on the floors of the trenches.
Inventors
- 👤 Werner Loose
- 👤 Jacek Korec
- 👤 Ekkehard Niemann
- 👤 Alfred Boos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:54
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D30/00; H10D30/80; H10D30/83; H10D30/831; H10D62/00; H10D62/80; H10D62/83; H10D62/832; H10D62/8325; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D30/01; H10D30/051
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
97 words
An arrangement of SiC field-effect transistors, each having a source contact, a gate contact and a drain contact, formed on a semiconductor wafer and wherein: the source contacts are disposed on an upper surface of the semiconductor wafer, the drain contacts are disposed on a flat underside of the semiconductor wafer, the gate contacts are disposed in trenches formed in the semiconductor wafer and extend from the upper surface and which surround respective source electrodes of the field-effect transistors in ring fashion, and the gate contacts are connected to one another on bottom faces of the trenches.
Claim 2
Dependent Claim
97 words
An arrangement of SiC field-effect transistors, each having a source contact, a gate contact and a drain contact, formed on a semiconductor wafer and wherein: the source contacts are disposed on an upper surface of the semiconductor wafer, the drain contacts are disposed on a flat underside of the semiconductor wafer, the gate contacts are disposed in trenches formed in the semiconductor wafer and extend from the upper surface and which surround respective source electrodes of the field-effect transistors in ring fashion, and the gate contacts are connected to one another on bottom faces of the trenches.
Claim 3
Dependent Claim
32 words
An arrangement of SiC field-effect transistors according to claim 1, wherein the trenches have side walls which form an angle of 60° to 90° with the upper surface of the semiconductor wafer.
Claim 4
Dependent Claim
31 words
An arrangement of field-effect transistors according to claim 1, wherein the side walls of the trenches form an angle of 70° to 85° with the upper surface of the semiconductor wafer.
Claim 5
Dependent Claim
25 words
An arrangement of field-effect transistors according to claim 1, wherein the thickness of a layer extending between drain and source is 3 to 1000 μm.
Claim 6
Dependent Claim
25 words
An arrangement of field-effect transistors according to claim 1, wherein the thickness of a layer extending between source and drain is 3 to 25 μm.
Claim 7
Dependent Claim
25 words
An arrangement of field-effect transistors according to claim 1, wherein the thickness of a layer extending between source and drain is 3 to 100 μm.
Claim 8
Dependent Claim
20 words
An arrangement of field-effect transistors according to claim 1 wherein the depth of the trench is 2 to 10 μm.
Claim 9
Dependent Claim
20 words
An arrangement of field-effect transistors according to claim 1, wherein the depth of the trench is 4 to 8 μm.
Claim 10
Dependent Claim
70 words
An arrangement of SiC field effect transistors according to claim 1 wherein: the wafer comprises a SiC layer of one conductivity type disposed on a low resistivity substrate and a highly doped source electrode SiC layer of the same conductivity type formed on the SiC layer; the trench is formed in the SiC layer; and the gate electrode is formed directly on at least the bottom faces of the trenches.
Claim 11
Dependent Claim
36 words
An arrangement of SiC field effect transistors according to claim 9 wherein the sidewalls and bottom of the trenches are doped to be of the opposite conductivity type from the conductivity type of the SiC layer.
Claim 12
Dependent Claim
122 words
Method of producing an arrangement of SiC field-effect transistors having source contacts, drain contacts and gate contacts, wherein the gate regions are disposed in trenches, according to claim 1, wherein: an epitaxial layer of SiC is deposited on a low-resistance substrate on whose underside a drain electrode is disposed, an n + zone is produced on the surface of this SiC layer, island-shaped regions surrounded by the trenches are etched out of this layer with the aid of a mask, the gate contact is produced by metallization, the mask is removed, the trenches then are filled by an insulator, the contacting of the source electrodes is prepared by at least one of polishing and etching and, finally, the source contact is applied.
Claim 13
Dependent Claim
27 words
Method according to claim 11, wherein the side walls and bottom of the trenches are doped by p + ion implantation prior to producing the gate contact.
Claim 14
Dependent Claim
29 words
Method according to claim 12, wherein an implantation with a trivalent element is performed with energies E<2 MeV, wherein the ions impact upon the silicon carbide surface from above.
Claim 15
Dependent Claim
34 words
Method according to claim 12, wherein when the ions impact at an angle, the semiconductor wafer rotates so that uniformly-doped regions are created in the region of the trench side walls and trench bottom.
Claim 16
Dependent Claim
19 words
Method according to claim 11, wherein the mask is characterized by a structural width of 0.5 to 3 μm.
Claim 17
Dependent Claim
19 words
Method according to claim 11, wherein the mask comprises an insulator which is produced from Si, O and/or N.
Claim 18
Dependent Claim
18 words
Method according to claim 11, wherein the mask is etched by a wet-chemical etching process and lightly underetched.
Claim 19
Dependent Claim
49 words
Method according to claim 11, wherein the trenches are produced using a gas mixture of Cl 2 /SiCl 4 /O 2 /Ar, or N 2 instead of argon, by means of a so-called RIE process, wherein concentrations of the gases are in the sequence of the enumeration 40/20/4.2/10 sccm.
Claim 20
Dependent Claim
27 words
Method according to claim 11, wherein an etching process is performed until the depth of the trench is 2-10 μm and the width is approximately 3-10 μm.
Claim 21
Dependent Claim
30 words
Method according to claim 11, wherein a thin metal layer resulting at the trench side walls by metallization of the gate contacts is etched away with an additional etching process.
Claim 22
Dependent Claim
15 words
Method according to claim 11, wherein the trenches are filled by CVD SiO 2 .
Claim 23
Dependent Claim
22 words
Method according to claim 11, wherein the mask is structured such that a hexagonal structure of the source contacts and trenches results.
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| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
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