Low voltage, switched capacitance circuit employing switched operational amplifiers with maximized voltage swing

Claim 2

An integrated circuit switched capacitance stage, connected to be powered from a supply voltage and a ground, comprising; a first operational amplifier connected to receive an input signal, and to intermittently drive a first terminal of a switched capacitor in dependence on said input signal, during at least a first clock phase but not during a second clock phase; a bias capacitor having one terminal thereof connected to a second terminal of said switched capacitor and the other terminal thereof switchably connected both to the supply voltage and to the ground; a first switch connecting the output of said first operational amplifier to a first constant voltage during at least said second clock phase but not during said first clock phase; an additional switch connected to switch said second terminal of the switched capacitor to a second constant voltage during at least said first clock phase but not during said second clock phase; and a second operational amplifier operatively connected to receive a voltage on said second terminal of said switched capacitor, and to provide an output signal on an output of said second operational amplifier accordingly during at least said second clock phase but not during said first clock phase; whereby said bias capacitor biases an output voltage of said first operational amplifier toward a value intermediate between the supply voltage and the ground for providing a maximum voltage swing.

Claim 3

The integrated circuit of claim 1, wherein said other terminal of said bias capacitor is connected to said power supply during said first clock phase, and to ground during said second clock phase.

Claim 4

The integrated circuit of claim 1, wherein said first switch consists of a single transistor.

Claim 5

The integrated circuit of claim 1, further comprising a further capacitor connected between said output of said second operational amplifier and an inverting input of said second operational amplifier.

Claim 6

The integrated circuit of claim 1, further comprising a further capacitor connected between said output of said first operational amplifier and an inverting input of said first operational amplifier.

Claim 7

The integrated circuit of claim 1, wherein said output signal of said second operational amplifier is differential.

Claim 8

The integrated circuit of claim 1, wherein said additional switch is on during at least a third clock phase which is not part of said first clock phase nor of said second clock phase.

Claim 9

The integrated circuit of claim 1, wherein said first constant voltage is ground.

Claim 10

The integrated circuit of claim 1, wherein said first constant voltage is the supply voltage.

Claim 11

The integrated circuit of claim 1, wherein said second constant voltage is ground.

Claim 12

The integrated circuit of claim 1, wherein said additional switch is bypassed by an additional capacitor.

Claim 13

The integrated circuit of claim 1, wherein said bias capacitor biases an output voltage of said first operational amplifier toward a value approximately halfway between the supply voltage and ground.

Claim 14

The integrated circuit of claim 1, further comprising a further switch interposed between said second terminal of said switched capacitor and said second operational amplifier, said further switch being on during at least a second clock phase but not during a first clock phase.

Claim 15

An integrated switched capacitance circuit, connected to be powered from a supply voltage and a ground, comprising: a first switched operational amplifier connected to receive an input signal, and to intermittently drive a first terminal of a switched capacitor; a bias capacitor having one terminal thereof connected to a second terminal of said switched capacitor and the other terminal thereof switchably connected both to the supply voltage and to the ground; a first switch connecting the output of said first operational amplifier to a first constant voltage during a turn-off phase of said operational amplifier; an additional switch connected to switch said second terminal of the switched capacitor to ground during a turn-on phase of said operational amplifier; whereby said bias capacitor biases an output voltage of said first operational amplifier toward a value intermediate between the supply voltage and the ground for providing a maximum voltage swing.

Claim 16

An integrated switched capacitance circuit, connected to be powered from a supply voltage and a ground, comprising: a first switched operational amplifier connected to receive an input signal, and to intermittently drive a first terminal of a switched capacitor; a bias capacitor having one terminal thereof connected to a second terminal of said switched capacitor and the other terminal thereof switchably connected both to the supply voltage and to the ground; a first switch connecting the output of said first operational amplifier to a first constant voltage during a turn-off phase of said operational amplifier; an additional switch connected to switch said second terminal of the switched capacitor to ground during a turn-on phase of said operational amplifier; whereby said bias capacitor biases an output voltage of said first operational amplifier toward a value intermediate between the supply voltage and the ground for providing a maximum voltage swing.

Claim 17

The integrated circuit of claim 14, wherein said other terminal of said bias capacitor is connected to said power supply during said first clock phase, and to ground during said second clock phase.

Claim 18

The integrated circuit of claim 14, wherein said first constant voltage is ground.

Claim 19

The integrated circuit of claim 14, wherein said first constant voltage is the supply voltage.

Claim 20

The integrated circuit of claim 14, wherein said additional switch is an NMOS transistor having a source terminal thereof connected to ground.

Claim 21

The integrated circuit of claim 14, wherein said additional switch is bypassed an additional capacitor.

Claim 22

The integrated circuit of claim 14, wherein said bias capacitor biases an output voltage of said first operational amplifier toward a value approximately halfway between the supply voltage and ground.

Claim 23

An integrated circuit switched capacitance differential stage, connected to be powered from a supply voltage and a ground, comprising: a first fully differential amplifier connected to receive respective differential input signals, and to provide respective differential output signals in dependence on said respective input signals, during at least a first clock phase but not during a second clock phase; first and second circuit branches, each including a respective switched capacitor having a first terminal connected to be driven by a respective side of said differential output signal, and a respective bias capacitor having one terminal thereof connected to a second terminal of said respective switched capacitor, and the other terminal thereof switchably connected both to the supply voltage and to ground, a respective first switch connecting an output of said first fully differential amplifier to a first constant voltage during at least said second clock phase but not during said first clock phase; an additional respective switch connected to switch said second terminal of said respective switched capacitor to a second constant voltage during at least said first clock phase but not during said second clock phase; and a second fully differential amplifier connected to receive a respective voltage on said second terminal of each of said respective switched capacitors and to provide a respective output signal accordingly, during at least said second clock phase but not during said first clock; whereby said respective bias capacitor biases a respective output voltage of said first switched operational amplifier toward a value intermediate between the supply voltage and the around for providing a maximum voltage swing.

Claim 24

An integrated circuit switched capacitance differential stage, connected to be powered from a supply voltage and a ground, comprising: a first fully differential amplifier connected to receive respective differential input signals, and to provide respective differential output signals in dependence on said respective input signals, during at least a first clock phase but not during a second clock phase; first and second circuit branches, each including a respective switched capacitor having a first terminal connected to be driven by a respective side of said differential output signal, and a respective bias capacitor having one terminal thereof connected to a second terminal of said respective switched capacitor, and the other terminal thereof switchably connected both to the supply voltage and to ground, a respective first switch connecting an output of said first fully differential amplifier to a first constant voltage during at least said second clock phase but not during said first clock phase; an additional respective switch connected to switch said second terminal of said respective switched capacitor to a second constant voltage during at least said first clock phase but not during said second clock phase; and a second fully differential amplifier connected to receive a respective voltage on said second terminal of each of said respective switched capacitors and to provide a respective output signal accordingly, during at least said second clock phase but not during said first clock; whereby said respective bias capacitor biases a respective output voltage of said first switched operational amplifier toward a value intermediate between the supply voltage and the around for providing a maximum voltage swing.

Claim 25

The integrated circuit of claim 21, wherein said other terminal of each said respective bias capacitor is connected to said power supply during said first clock phase, and to the ground during said second clock phase.

Claim 26

The integrated circuit of claim 21, wherein each said respective first switch consists of a single transistor.

Claim 27

The integrated circuit of claim 21, wherein said respective output signal of said second fully differential amplifier is differential.

Claim 28

The integrated circuit of claim 21, wherein each said respective additional switch is on during at least a third clock phase which is neither part of said first clock phase nor of said second clock phase.

Claim 29

The integrated circuit of claim 21, wherein said first constant voltage is the ground.

Claim 30

The integrated circuit of claim 21, wherein said first constant voltage is the supply voltage.

Claim 31

The integrated circuit of claim 21, wherein said second constant voltage is the ground.

Claim 32

The integrated circuit of claim 21, wherein each said respective additional switch is bypassed by a respective additional capacitor.

Claim 33

The integrated circuit of claim 21, wherein each said respective bias capacitor biases an output voltage of said first operational amplifier toward a value approximately halfway between the supply voltage and the ground.

Claim 34

The integrated circuit of claim 21, wherein each said branch further comprises a respective further switch interposed between said second terminal of said respective switched capacitor and said second fully differential amplifier, said further switch being on during at least a second clock phase but not during a first clock phase.

Claim 35

A switched capacitance circuit comprising: a first switched operational amplifier receiving an input signal and connected to an input of a switched capacitor; a first means for biasing a first output DC voltage of said first switched operational amplifier and for setting a level of said first output DC voltage of said first switched operational amplifier to a value about half of a supply voltage, said first means comprising a bias capacitor having one terminal thereof connected to an output of said switched capacitor and the other terminal thereof connected through a first switch to a power supply and through a second switch to ground; a third switch switching an output of said first switched operational amplifier to the supply voltage during a turn-off phase of said first switched operational amplifier; and a fourth switch switching said output of the switched capacitor to the ground during a turn-on phase of said first switched operational amplifier; whereby said bias capacitor biases said output DC voltage of said first switched operational amplifier toward a value intermediate between the supply voltage and the ground for providing a maximum voltage swing.

Claim 36

A switched capacitance circuit comprising: a first switched operational amplifier receiving an input signal and connected to an input of a switched capacitor; a first means for biasing a first output DC voltage of said first switched operational amplifier and for setting a level of said first output DC voltage of said first switched operational amplifier to a value about half of a supply voltage, said first means comprising a bias capacitor having one terminal thereof connected to an output of said switched capacitor and the other terminal thereof connected through a first switch to a power supply and through a second switch to ground; a third switch switching an output of said first switched operational amplifier to the supply voltage during a turn-off phase of said first switched operational amplifier; and a fourth switch switching said output of the switched capacitor to the ground during a turn-on phase of said first switched operational amplifier; whereby said bias capacitor biases said output DC voltage of said first switched operational amplifier toward a value intermediate between the supply voltage and the ground for providing a maximum voltage swing.

Claim 37

The circuit of claim 32, further comprising a buffer capacitor connected between said output of the switched capacitor and the ground.

Claim 38

The circuit of claim 32, further comprising an output switched amplifier composed of a second switched operational amplifier having a non inverting input connected to the ground and an inverting input functionally connected to said output of the switched capacitor through a fifth switch.

Claim 39

The circuit of claim 34, wherein each of said first switch and said third switch is realized with a P-channel field effect transistor, and each of said second, fourth, and fifth switches is realized with an N-channel field effect transistor.

Claim 40

The circuit of claim 32, wherein said first switched operation amplifier is a fully differential amplifier having said first and a second output DC voltage, said circuit further comprising a second means for biasing said second output DC voltage of said switched operational amplifier and for setting the level of said second output DC voltage of said first switched operational amplifier to a value about half of said supply voltage.

Claim 43

The method of claim 37, wherein said other terminal of said bias capacitor is connected to said power supply during said first clock phase, and to ground during said second clock phase.

Claim 44

The method of claim 37, wherein said first and second clock phases are strictly non-overlapping.

Claim 45

The method of claim 37, wherein said bias capacitor biases an output voltage of said first operational amplifier toward a value approximately halfway between the supply voltage and ground.

Claim 48

The method of claim 41, wherein said other terminal of said bias capacitor is connected to said power supply during said first clock phase, and to ground during said second clock phase.

Claim 49

The method of claim 41, wherein said bias capacitor biases an output voltage of said first operational amplifier toward a value approximately halfway between the supply voltage and ground.

Claim 52

The method of claim 44, further comprising the additional steps of connecting the output of said first operational amplifier to the ground during at least said second clock phase but not during said first clock phase; and connecting said second terminal of said switched capacitor to a constant voltage during at least said first clock phase but not during said second clock phase.

Claim 53

The method of claim 44, wherein said other terminal of said bias capacitor is connected to said power supply during said first clock phase, and to ground during said second clock phase.

Claim 54

The method of claim 44, wherein said first and second clock phases are strictly non-overlapping.

Claim 55

The method of claim 44, wherein said bias capacitor biases an output voltage of said first operational amplifier toward a value approximately halfway between the supply voltage and ground.