Scalable multimedia network

Claim 2

In a communication system comprising first and second uni-directional buses oppositely directed, a plurality of units, each said unit and at least one end unit coupled to both buses, said at least one end unit for generating cells on said first bus, said cells including request, idle, empty, and payload cells, at least another end unit for connecting said first bus to said second bus, a method for controlling transmission of said cells, including the steps of: generating at said at least one end unit a cell pattern comprising a series consisting of a request cell of first priority followed by N empty cells of first priority, said series repeating x times and y idle cells; transmitting said cell pattern at said at least one end unit onto said first bus; receiving said cell pattern at one of said units on said first bus; modifying said request cell at said one unit in response to at least one packet having been collected in a priority queue in said unit; transmitting said modified request cell at said one unit onto said first bus; receiving said request cell at said at least one end unit on said second bus and modifying a priority counter in response to a logical value of said request cell; generating said empty cells at said at least one end unit onto said first bus in response to a logical value of said priority counter.

Claim 3

Apparatus for interconnecting a first bus and a second bus having an upward path and a downward path, wherein said buses carry data formatted into cells, wherein said cells comprise request empty, payload and idle cells, comprising: a first decoder circuit for receiving a first serial input signal from said upward path of said second bus and for decoding said first serial input signal into a first N bit parallel signal; a first register for retiming said first N bit parallel signal; a detector circuit responsive to the output of said first register for detecting said empty cells; a first controller circuit for receiving packet data from said first bus and for writing said packet data into said empty cells, whereby said empty cells are transformed into said payload cells; an adder circuit for modifying said request cell in response to at least one packet having been collected in said first controller circuit; an arbiter multiplexer circuit for selecting among said first N bit parallel signal from said first register, said request cell modified by said adder circuit, and said payload cells from said first controller circuit, a first encoder circuit for encoding an output of said arbiter multiplexer circuit into a first M bit parallel signal and for converting said first M bit parallel signal into a first serial output signal and for transmitting said first serial output signal to said upward path of said second bus; a second decoder circuit for receiving a second serial input signal from said downward path of said second bus and for decoding said second serial input signal into a second N bit parallel signal; a second register for retiming said second N bit parallel signal; a second controller circuit for extracting said packet data from said payload cells and for transmitting said extracted packet data to said first bus; and a second encoder circuit for encoding said second N bit parallel signal into a second M bit parallel signal and for converting said second M bit parallel signal into a second serial output signal and for transmitting said second serial output signal to said downward path of said second bus.

Claim 4

Apparatus for interconnecting a first bus and a second bus having an upward path and a downward path, wherein said buses carry data formatted into cells, wherein said cells comprise request empty, payload and idle cells, comprising: a first decoder circuit for receiving a first serial input signal from said upward path of said second bus and for decoding said first serial input signal into a first N bit parallel signal; a first register for retiming said first N bit parallel signal; a detector circuit responsive to the output of said first register for detecting said empty cells; a first controller circuit for receiving packet data from said first bus and for writing said packet data into said empty cells, whereby said empty cells are transformed into said payload cells; an adder circuit for modifying said request cell in response to at least one packet having been collected in said first controller circuit; an arbiter multiplexer circuit for selecting among said first N bit parallel signal from said first register, said request cell modified by said adder circuit, and said payload cells from said first controller circuit, a first encoder circuit for encoding an output of said arbiter multiplexer circuit into a first M bit parallel signal and for converting said first M bit parallel signal into a first serial output signal and for transmitting said first serial output signal to said upward path of said second bus; a second decoder circuit for receiving a second serial input signal from said downward path of said second bus and for decoding said second serial input signal into a second N bit parallel signal; a second register for retiming said second N bit parallel signal; a second controller circuit for extracting said packet data from said payload cells and for transmitting said extracted packet data to said first bus; and a second encoder circuit for encoding said second N bit parallel signal into a second M bit parallel signal and for converting said second M bit parallel signal into a second serial output signal and for transmitting said second serial output signal to said downward path of said second bus.

Claim 5

The apparatus of claim 2 further comprising: a cell scheduler circuit for examining said cells contained in said second N bit parallel signal such that a count contained in each said request cell is maintained, a number of said empty cells responsive to said count are generated, and said request cell is generated following said generated empty cells.

Claim 6

The apparatus of claim 2 wherein N=32 and M=20.

Claim 7

The method of claim 1 wherein N=64, X=24, and Y=2.5.

Claim 8

The method of claim 1 further comprising decrementing said priority counter for each generated empty cell.

Claim 9

The method of claim 6 further comprising generating an empty cell of second priority at said one end unit onto said first bus in response to said priority counter reaching zero.

Claim 10

In a communication system comprising first and second buses, a plurality of units, each said unit and an end unit coupled to both buses, said end unit for generating cells on said first bus, said cells including request, idle, empty, and payload cells, a method for controlling transmission of said cells, including the steps of: generating at said end unit a cell pattern; transmitting said cell pattern at said end unit onto said first bus; modifying said cell pattern at one of said units in response to at least one packet having been collected in a priority queue in said one unit; transmitting said modified cell pattern at said one unit onto said first bus; and receiving said modified cell pattern at said end unit on said second bus and modifying a priority counter in response to a logical value of said cell pattern.

Claim 11

In a communication system comprising first and second buses, a plurality of units, each said unit and an end unit coupled to both buses, said end unit for generating cells on said first bus, said cells including request, idle, empty, and payload cells, a method for controlling transmission of said cells, including the steps of: generating at said end unit a cell pattern; transmitting said cell pattern at said end unit onto said first bus; modifying said cell pattern at one of said units in response to at least one packet having been collected in a priority queue in said one unit; transmitting said modified cell pattern at said one unit onto said first bus; and receiving said modified cell pattern at said end unit on said second bus and modifying a priority counter in response to a logical value of said cell pattern.

Claim 12

The method of claim 8 wherein the cell pattern comprises a series consisting of a request cell of first priority followed by N empty cells of first priority, said series repeating x times and y idle cells.

Claim 13

The method of claim 9 further comprising generating said empty cells at said end unit onto said first bus in response to a logical value of said priority counter.

Claim 14

The method of claim 9 wherein N=64, X=24, and Y=2.5.

Claim 15

The method of claim 10 further comprising decrementing said priority counter for each generated empty cell.

Claim 16

The method of claim 12 further comprising generating an empty cell of second priority at said end unit onto said first bus in response to said priority counter reaching zero.

Claim 17

Apparatus for interconnecting a first bus and a second bus having an upward path and a downward path, wherein said buses carry data formatted into cells, wherein said cells comprise request empty, payload and idle cells, comprising: a first decoder circuit for receiving a first serial input signal from said upward path of said second bus and for decoding said first serial input signal; a detector circuit coupled to said first decoder circuit for detecting said empty cells; a first controller circuit for receiving packet data from said first bus and for writing said packet data into said empty cells, whereby said empty cells are transformed into said payload cells; an adder circuit for modifying said request cell in response to at least one packet having been collected in said first controller circuit; an arbiter multiplexer circuit for selecting among said first decoded serial input signal, said request cell modified by said adder circuit, and said payload cells from said first controller circuit; a first encoder circuit for encoding an output of said arbiter multiplexer circuit into a first serial output signal and for transmitting said first serial output signal to said upward path of said second bus; a second decoder circuit for receiving a second serial input signal from said downward path of said second bus and for decoding said second serial input signal; a second controller circuit for extracting said packet data from said payload cells and for transmitting said extracted packet data to said first bus; and a second encoder circuit for encoding said second serial input signal into a second serial output signal and for transmitting said second serial output signal to said downward path of said second bus.

Claim 18

Apparatus for interconnecting a first bus and a second bus having an upward path and a downward path, wherein said buses carry data formatted into cells, wherein said cells comprise request empty, payload and idle cells, comprising: a first decoder circuit for receiving a first serial input signal from said upward path of said second bus and for decoding said first serial input signal; a detector circuit coupled to said first decoder circuit for detecting said empty cells; a first controller circuit for receiving packet data from said first bus and for writing said packet data into said empty cells, whereby said empty cells are transformed into said payload cells; an adder circuit for modifying said request cell in response to at least one packet having been collected in said first controller circuit; an arbiter multiplexer circuit for selecting among said first decoded serial input signal, said request cell modified by said adder circuit, and said payload cells from said first controller circuit; a first encoder circuit for encoding an output of said arbiter multiplexer circuit into a first serial output signal and for transmitting said first serial output signal to said upward path of said second bus; a second decoder circuit for receiving a second serial input signal from said downward path of said second bus and for decoding said second serial input signal; a second controller circuit for extracting said packet data from said payload cells and for transmitting said extracted packet data to said first bus; and a second encoder circuit for encoding said second serial input signal into a second serial output signal and for transmitting said second serial output signal to said downward path of said second bus.

Claim 19

The apparatus of claim 14 further comprising: a cell scheduler circuit for examining said cells contained in said second serial input signal such that a count contained in each said request cell is maintained, a number of said empty cells responsive to said count are generated, and said request cell is generated following said generated empty cells.