US5734819A
Expired / Lapsed
US
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Method and apparatus for validating system operation
Assignee: International Business Machines Corp
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Filing: 1994-10-12
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Granted: 1998-03-31
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Expires: 2014-10-12
Abstract
Abstract A method and apparatus for providing system operation validation is disclosed. The method and apparatus for validation operates within a computer system comprising a central processing unit coupled to a programmable memory, and to a system device. The programmable memory may store programs and instructions executable on the CPU and a non-volatile memory is also provided for access by the CPU. The system operation validation is provided by a chip identifier located within a device memory within the system device, which memory also serves as a chip identifier register. Selected information stored within the non-volatile memory is used, along with the chip identifier, to generate a first encryption code associated with the system device. An encryption key is used to generate a second encryption code associated with the computer system. The first and second encryption codes are matched to provide a first level system operation validation. A second chip identifier is generated, which identifier is associated with the computer system. Both chip identifiers are compared to provide a second level system operation validation.
Inventors
- 👤 David Otto Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:17
CPC Classifications
G; G06; G06F; G06F21/00; G06F21/50; G06F21/57; G06F21/10; G06F21/12; G06F21/121; G06F21/60; G06F21/64; G06F21/70; G06F21/71; G06F21/73; G06F2207/00; G06F2207/72; G06F2207/7219
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
137 words
In a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, a system device, coupled to said CPU, and a non-volatile memory, coupled to said CPU, a system operation validator comprising: a chip identifier located in a chip identifier register within said system device; means for utilizing selected information stored within said non-volatile memory and said chip identifier to generate a first encryption code associated with said system device; an encryption key stored within said programmable memory; means for generating a second encryption code associated with said CPU using said encryption key, wherein said encryption codes must match for system operation validation; means for generating a second chip identifier associated with said CPU, wherein said chip identifiers must match for system operation validation.
Claim 2
Dependent Claim
137 words
In a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, a system device, coupled to said CPU, and a non-volatile memory, coupled to said CPU, a system operation validator comprising: a chip identifier located in a chip identifier register within said system device; means for utilizing selected information stored within said non-volatile memory and said chip identifier to generate a first encryption code associated with said system device; an encryption key stored within said programmable memory; means for generating a second encryption code associated with said CPU using said encryption key, wherein said encryption codes must match for system operation validation; means for generating a second chip identifier associated with said CPU, wherein said chip identifiers must match for system operation validation.
Claim 3
Dependent Claim
31 words
The invention according to claim 1 wherein said system device is a field-replaceable unit and said chip identifier is a chip serial number and said non-volatile memory is a semiconductor-type device.
Claim 4
Dependent Claim
24 words
The invention according to claim 1 wherein said chip identifier is a chip serial number and said non-volatile memory is a magnetic media-type device.
Claim 5
Dependent Claim
23 words
The invention according to claim 1 wherein said chip identifier is a chip serial number and said non-volatile memory is an optical-type device.
Claim 6
Dependent Claim
33 words
The invention according to claim 1 wherein said chip identifier is a chip serial number and said non-volatile memory is a tape-drive device with said information being stored as microcode on a tape.
Claim 7
Dependent Claim
16 words
The invention according to claim 1 wherein said encryption codes are comprised of message authentication codes.
Claim 8
Dependent Claim
142 words
In a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, a system device, coupled to said CPU, and a non-volatile memory, coupled to said CPU, a method for validating system operation comprising the steps of: locating a chip identifier within in a chip identifier register within said system device; utilizing selected information stored with said non-volatile memory and said chip identifier to generate a first encryption code associated with said system device; generating a second encryption code associated with said CPU using an encryption key; determining whether said encryption codes match for system operation validation; upon matching said encryption codes, generating a second chip identifier associated with said CPU; determining whether said chip identifiers match for system operation validation; upon matching said chip identifiers, granting system operation.
Claim 9
Dependent Claim
142 words
In a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, a system device, coupled to said CPU, and a non-volatile memory, coupled to said CPU, a method for validating system operation comprising the steps of: locating a chip identifier within in a chip identifier register within said system device; utilizing selected information stored with said non-volatile memory and said chip identifier to generate a first encryption code associated with said system device; generating a second encryption code associated with said CPU using an encryption key; determining whether said encryption codes match for system operation validation; upon matching said encryption codes, generating a second chip identifier associated with said CPU; determining whether said chip identifiers match for system operation validation; upon matching said chip identifiers, granting system operation.
Claim 10
Dependent Claim
31 words
The invention according to claim 7 wherein said system device is a field-replaceable unit and said chip identifier is a chip serial number and said non-volatile memory is an EPROM-type device.
Claim 11
Dependent Claim
23 words
The invention according to claim 7 wherein said chip identifier is a chip serial number and said non-volatile memory is a DASD-type device.
Claim 12
Dependent Claim
33 words
The invention according to claim 7 wherein said chip identifier is a chip serial number and said non-volatile memory is a tape-drive device with said information being stored as microcode on a tape.
Claim 13
Dependent Claim
16 words
The invention according to claim 7 wherein said encryption codes are comprised of message authentication codes.
References Cited (Backward Citations)
US4264782A
Cited
US4424573A
Cited
US4670857A
Cited
US4442486A
Cited
US4454594A
Cited
US4462076A
Cited
US4652990A
Cited
US4634807A
Cited
EP0175359A2
Cited
US4731748A
Cited
US4751667A
Cited
US4688169A
Cited
US4933969A
Cited
EP0302710A2
Cited
US4866769A
Cited
US5075805A
Cited
US5113518A
Cited
US4903299A
Cited
US5199066A
Cited
US5379433A
Cited
US5068894A
Cited
EP0425053A1
Cited
US5481672A
Cited
US5182770A
Cited
US5343524A
Cited
WO1993023807A1
Cited
US5287408A
Cited
US5386468A
Cited
US5282247A
Cited
US5276738A
Cited
US5392356A
Cited
US5388212A
Cited
US5483658A
Cited
US5337357A
Cited
US5402492A
Cited
US5416840A
Cited
US5546463A
Cited
US5530753A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |