US5732235A
Expired / Lapsed
US
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Method and system for minimizing the number of cycles required to execute semantic routines
Assignee: International Business Machines Corp
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Filing: 1996-01-25
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Granted: 1998-03-24
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Expires: 2016-01-25
Abstract
Abstract A system and method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions. Each of the semantic routines includes a block of host instructions for performing the function of the corresponding guest instruction, and the last instruction in each of the semantic routines is a branch instruction. The method and system first determines the block length of each of the semantic routines. When a first guest instruction is encountered, the block of instructions in a first semantic routine corresponding to a guest instruction is executed. The block length of first semantic routine is then used to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.
Inventors
- 👤 James Allan Kahle
- 👤 Soummya Mallick
- 👤 Larry Bryce Phillips
- 👤 Russell Adley Reininger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30174; G06F9/38; G06F9/3877; G06F9/3879; G06F9/44; G06F9/455; G06F9/45504
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
114 words
A method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions, each of the semantic routines including a block of host instructions, wherein the last instruction in each of the semantic routines is a branch instruction, the method comprising the steps of: (a) determining a block length for each of the semantic routines; (b) executing the block of instructions in a first semantic routine corresponding to a first guest instruction; and (c) using the block length of the first semantic routine to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.
Claim 2
Independent Claim
114 words
A method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions, each of the semantic routines including a block of host instructions, wherein the last instruction in each of the semantic routines is a branch instruction, the method comprising the steps of: (a) determining a block length for each of the semantic routines; (b) executing the block of instructions in a first semantic routine corresponding to a first guest instruction; and (c) using the block length of the first semantic routine to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.
Claim 3
Dependent Claim
22 words
A method as in claim 1 wherein step (a) further includes the step of: (a1) storing the block length in a counter.
Claim 4
Dependent Claim
29 words
A method as in claim 2 wherein step (b) further includes the step of: (b1) decrementing the counter when each of the instructions in the semantic routine is executed.
Claim 5
Dependent Claim
34 words
A method as in claim 3 wherein step (c) further includes the step of: (c1) fetching the first instruction of the second semantic routine when the counter is less than or equal to one.
Claim 6
Independent Claim
141 words
A method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions, each of the semantic routines including a block of host instructions, wherein the last instruction in each of the semantic routines is a branch instruction, the method comprising the steps of: (a) determining a block length of a first semantic routine; (b) executing the block of instructions in the first semantic routine by performing a fetch, decode, and execute cycle on each of the instructions in the block of instructions; (c) decrementing the block length when each of the instructions in the first semantic routine is fetched; and (d) using the block length of first semantic routine to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.
Claim 7
Independent Claim
141 words
A method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions, each of the semantic routines including a block of host instructions, wherein the last instruction in each of the semantic routines is a branch instruction, the method comprising the steps of: (a) determining a block length of a first semantic routine; (b) executing the block of instructions in the first semantic routine by performing a fetch, decode, and execute cycle on each of the instructions in the block of instructions; (c) decrementing the block length when each of the instructions in the first semantic routine is fetched; and (d) using the block length of first semantic routine to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.
Claim 8
Dependent Claim
22 words
A method as in claim 5 wherein step (a) further includes the step of: (a1) storing the block length in a counter.
Claim 9
Dependent Claim
29 words
A method as in claim 6 wherein step (c) further includes the step of: (c1) decrementing the counter when each of the instructions in the semantic routine is executed.
Claim 10
Dependent Claim
34 words
A method as in claim 7 wherein step (c) further includes the step of: (c1) fetching the first instruction of the second semantic routine when the counter is less than or equal to one.
Claim 11
Dependent Claim
234 words
An emulation assist unit for assisting a host processor to emulate a set of guest instructions using semantic routines, each of the semantic routines being stored at specific addresses in memory and including a block of instructions wherein the last instruction in the block is a branch instruction, each of the semantic routines further having a block length, the emulation assist unit comprising: a cache for associating each of the semantic routines with a memory address; decode means for parsing each of the guest instructions to determine instruction type; tag generation means for generating a tag from the instruction type in order to index the cache; a queue for storing entries from the cache indexed by the tag, each of the entries in the queue include an offset field, a data field, and a length field, wherein the offset field is a pointer to the memory address of one of the semantic routines, and the length field contains the block length of the corresponding semantic routine; and the processor including means responsive to a first entry in the queue for executing a first semantic routine located at the memory address indicated by the offset field, and means for using the block length to determine when to execute a second semantic routine from a second entry in the queue without fetching and decoding the branch instruction of the first semantic routine, thereby saving processor cycles.
Claim 12
Dependent Claim
234 words
An emulation assist unit for assisting a host processor to emulate a set of guest instructions using semantic routines, each of the semantic routines being stored at specific addresses in memory and including a block of instructions wherein the last instruction in the block is a branch instruction, each of the semantic routines further having a block length, the emulation assist unit comprising: a cache for associating each of the semantic routines with a memory address; decode means for parsing each of the guest instructions to determine instruction type; tag generation means for generating a tag from the instruction type in order to index the cache; a queue for storing entries from the cache indexed by the tag, each of the entries in the queue include an offset field, a data field, and a length field, wherein the offset field is a pointer to the memory address of one of the semantic routines, and the length field contains the block length of the corresponding semantic routine; and the processor including means responsive to a first entry in the queue for executing a first semantic routine located at the memory address indicated by the offset field, and means for using the block length to determine when to execute a second semantic routine from a second entry in the queue without fetching and decoding the branch instruction of the first semantic routine, thereby saving processor cycles.
Claim 13
Dependent Claim
20 words
An emulation assist unit as in claim 9 wherein the data field includes immediate data from the corresponding guest instruction.
Claim 14
Dependent Claim
19 words
An emulation assist unit as in claim 10 wherein the semantic routines are stored sequentially in a semantic buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |