US5732224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system having a dedicated multimedia engine including multimedia memory
Assignee: Advanced Micro Devices Inc
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Filing: 1997-06-18
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Granted: 1998-03-24
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Expires: 2017-06-18
Abstract
Abstract A computer system optimized for real-time applications which provides increased performance for real-time applications over current computer architectures. The system includes a dedicated multimedia engine coupled directly to the main memory which performs real-time operations, including audio and video functions, as well as others. The multimedia engine includes multimedia memory and one or more DSP (digital signal processor) engines. The DSP engines may comprise either dedicated audio or video engines or general purpose DSP engines. The DSP engines couple through one or more I/O channels to respective video, audio and communication ports. The multimedia engine includes video ports for coupling to a video monitor, audio ports for coupling to speakers and one or more communication ports. The multimedia memory in the multimedia engine comprises a portion of the main memory address space. Thus the multimedia is used for real-time or multimedia data and is also used by the CPU as overflow memory space.
Inventors
- 👤 Dale Gulick
- 👤 Andy Lambrecht
- 👤 Mike Webb
- 👤 Larry Hewitt
- 👤 Brian Barnes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:16
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
223 words
A computer system, comprising: a CPU; chip set logic coupled to the CPU, wherein the chip set logic includes arbitration logic and wherein the chip set logic includes expansion bus bridge logic for coupling to an expansion bus; an expansion bus coupled to the chip set logic; one or more peripheral devices coupled to the expansion bus; main memory coupled to the chip set logic which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the chip set logic, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and to said chip set logic and a second port; one or more DSP (digital signal processor) engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; one or more input/output channels coupled to said one or more DSP engines for transmitting data; a video port coupled to at least one of said one or more input/output channels, wherein said video port is adapted for coupling to a video monitor; an audio port coupled to at least one of said one or more input/output channels, wherein said audio port is adapted for transferring audio data.
Claim 2
Dependent Claim
223 words
A computer system, comprising: a CPU; chip set logic coupled to the CPU, wherein the chip set logic includes arbitration logic and wherein the chip set logic includes expansion bus bridge logic for coupling to an expansion bus; an expansion bus coupled to the chip set logic; one or more peripheral devices coupled to the expansion bus; main memory coupled to the chip set logic which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the chip set logic, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and to said chip set logic and a second port; one or more DSP (digital signal processor) engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; one or more input/output channels coupled to said one or more DSP engines for transmitting data; a video port coupled to at least one of said one or more input/output channels, wherein said video port is adapted for coupling to a video monitor; an audio port coupled to at least one of said one or more input/output channels, wherein said audio port is adapted for transferring audio data.
Claim 3
Dependent Claim
35 words
The computer system of claim 1, wherein said CPU is adapted for generating addresses within an address space, wherein said memory for storing multimedia data and said main memory are addressable within said address space.
Claim 4
Dependent Claim
35 words
The computer system of claim 2, wherein said address space includes a first address space portion and a second address space portion, wherein said multimedia data is stored only in said second address space portion.
Claim 5
Dependent Claim
22 words
The computer system of claim 1, wherein said memory for storing multimedia data and said main memory comprise a common address space.
Claim 6
Dependent Claim
25 words
The computer system of claim 1, wherein at least one of said one or more DSP engines comprises a video engine for manipulating video data.
Claim 7
Dependent Claim
39 words
The computer system of claim 5, wherein at least one of said one or more input/output channels is coupled between said video engine and said video port and transfers video data from said video engine to said video port.
Claim 8
Dependent Claim
25 words
The computer system of claim 1, wherein at least one of said one or more DSP engines comprises an audio engine for manipulating audio data.
Claim 9
Dependent Claim
39 words
The computer system of claim 7, wherein at least one of said one or more input/output channels is coupled between said audio engine and said audio port and transfers audio data from said audio engine to said audio port.
Claim 10
Dependent Claim
64 words
The computer system of claim 1, wherein said arbitration logic is coupled to said CPU, said expansion bus, said main memory and said multimedia engine, and wherein said arbitration logic receives main memory access requests from each of said CPU, said expansion bus, and said multimedia engine and grants main memory access to either of said CPU, said expansion bus, or said multimedia engine.
Claim 11
Dependent Claim
38 words
The computer system of claim 9, wherein said arbitration logic receives multimedia memory access requests from each of said CPU and said multimedia engine and grants multimedia memory access to either of said CPU or said multimedia engine.
Claim 12
Dependent Claim
28 words
The computer system of claim 1, wherein said multimedia engine further comprises: a direct memory access engine for transferring data from said main memory to said multimedia memory.
Claim 13
Dependent Claim
218 words
A computer system, comprising: a CPU, wherein said CPU generates addresses in an address space; chip set logic coupled to the CPU, wherein the chip set logic includes arbitration logic and wherein the chip set logic includes expansion bus bridge logic for coupling to an expansion bus; an expansion bus coupled to the chip set logic; one or more peripheral devices coupled to the expansion bus; main memory coupled to the chip set logic which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the chip set logic, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and to said chip set logic and a second port; one or more DSP (digital signal processor) engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; and one or more input/output channels coupled to said one or more DSP engines for transmitting data; wherein said main memory and said memory for storing multimedia data comprise a common address space; wherein said CPU is operable to access data in said main memory or said multimedia memory in said common address space.
Claim 14
Dependent Claim
218 words
A computer system, comprising: a CPU, wherein said CPU generates addresses in an address space; chip set logic coupled to the CPU, wherein the chip set logic includes arbitration logic and wherein the chip set logic includes expansion bus bridge logic for coupling to an expansion bus; an expansion bus coupled to the chip set logic; one or more peripheral devices coupled to the expansion bus; main memory coupled to the chip set logic which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the chip set logic, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and to said chip set logic and a second port; one or more DSP (digital signal processor) engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; and one or more input/output channels coupled to said one or more DSP engines for transmitting data; wherein said main memory and said memory for storing multimedia data comprise a common address space; wherein said CPU is operable to access data in said main memory or said multimedia memory in said common address space.
Claim 15
Dependent Claim
35 words
The computer system of claim 12, wherein said address space includes a first address space portion and a second address space portion, wherein said multimedia data is stored only in said second address space portion.
Claim 16
Dependent Claim
64 words
The computer system of claim 12, wherein said arbitration logic is coupled to said CPU, said expansion bus, said main memory and said multimedia engine, and wherein said arbitration logic receives main memory access requests from each of said CPU, said expansion bus, and said multimedia engine and grants main memory access to either of said CPU, said expansion bus, or said multimedia engine.
Claim 17
Dependent Claim
38 words
The computer system of claim 14, wherein said arbitration logic receives multimedia memory access requests from each of said CPU and said multimedia engine and grants multimedia memory access to either of said CPU or said multimedia engine.
Claim 18
Dependent Claim
28 words
The computer system of claim 12, wherein said multimedia engine further comprises: a direct memory access engine for transferring data from said main memory to said multimedia memory.
Claim 19
Dependent Claim
208 words
A computer system, comprising: a CPU, wherein said CPU generates addresses in an address space; chip set logic coupled to the CPU, wherein the chip set logic includes arbitration logic and wherein the chip set logic includes expansion bus bridge logic for coupling to an expansion bus; an expansion bus coupled to the chip set logic; one or more peripheral devices coupled to the expansion bus; main memory coupled to the chip set logic which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the chip set logic, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and to said chip set logic and a second port; one or more DSP engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; and one or more input/output channels coupled to said one or more DSP engines for transmitting data; wherein said main memory and said memory for storing multimedia data comprise a common address space; wherein said multimedia memory of said multimedia engine is operable to store non-multimedia data.
Claim 20
Dependent Claim
208 words
A computer system, comprising: a CPU, wherein said CPU generates addresses in an address space; chip set logic coupled to the CPU, wherein the chip set logic includes arbitration logic and wherein the chip set logic includes expansion bus bridge logic for coupling to an expansion bus; an expansion bus coupled to the chip set logic; one or more peripheral devices coupled to the expansion bus; main memory coupled to the chip set logic which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the chip set logic, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and to said chip set logic and a second port; one or more DSP engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; and one or more input/output channels coupled to said one or more DSP engines for transmitting data; wherein said main memory and said memory for storing multimedia data comprise a common address space; wherein said multimedia memory of said multimedia engine is operable to store non-multimedia data.
Claim 21
Dependent Claim
178 words
A computer system, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the CPU, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and a second port; one or more DSP (digital signal processor) engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; one or more input/output channels coupled to said one or more DSP engines for transmitting data; a video port coupled to at least one of said one or more input/output channels, wherein said video port is adapted for coupling to a video monitor; an audio port coupled to at least one of said one or more input/output channels, wherein said audio port is adapted for transferring audio data; wherein said memory for storing multimedia data and said main memory comprise a common address space.
Claim 22
Dependent Claim
178 words
A computer system, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; a multimedia engine coupled to the main memory and coupled to the CPU, wherein said multimedia engine comprises: memory for storing multimedia data, wherein said memory for storing multimedia data includes a first port coupled to said main memory and a second port; one or more DSP (digital signal processor) engines coupled to said second port of said memory, wherein said one or more DSP engines process said multimedia data stored in said multimedia memory; one or more input/output channels coupled to said one or more DSP engines for transmitting data; a video port coupled to at least one of said one or more input/output channels, wherein said video port is adapted for coupling to a video monitor; an audio port coupled to at least one of said one or more input/output channels, wherein said audio port is adapted for transferring audio data; wherein said memory for storing multimedia data and said main memory comprise a common address space.
Claim 23
Dependent Claim
35 words
The computer system of claim 18, wherein said CPU is adapted for generating addresses within an address space, wherein said memory for storing multimedia data and said main memory are addressable within said address space.
Claim 24
Dependent Claim
35 words
The computer system of claim 19, wherein said address space includes a first address space portion and a second address space portion, wherein said multimedia data is stored only in said second address space portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |