Serial rendering system with auto-synchronization on frame blanking

Claim 3

The method of claim 1, wherein all read operations are suspended when said write operations are suspended.

Claim 4

The method of claim 1, wherein said first and second buffer portions comprise distinct address ranges of said memory.

Claim 5

The method of claim 1, wherein write accesses to said second buffer portions are suspended when said write operations to said first buffer portion are suspended.

Claim 6

The method of claim 1, wherein said contents of said first buffer portion are cleared before said write operations are re-enabled.

Claim 7

The method of claim 1, wherein said each corresponding location in said first and second buffer portions comprise first and second pixel halves respectively.

Claim 8

The method of claim 1, wherein said memory further comprises a local buffer, said local buffer being operated independently of said first and second buffer portions.

Claim 9

The method of claim 1, wherein said memory comprises VRAM.

Claim 10

The method of claim 1, wherein said data is displayed from said second buffer portion when said first buffer portion is being written.

Claim 11

A memory control system comprising: a frame buffer memory having a first buffer portion and a second buffer portion; a control logic connected to receive and communicate a control signal comprising instruction and data segments; a read circuit connected between said control logic and said memory for reading from specific addresses specified by said control logic and returning the contents of said addresses to said control logic; a write circuit connected between said control logic and said memory for writing to or clearing specific addresses or groups of addresses in said memory according to said control logic; a suspend circuit connected to disable said write circuit when a suspend-until-frame-blank command is received by said control logic; wherein said control logic is connected to said write circuit to clear a specific said buffer portion and re-enable said write circuit when a frame-blank command is received.

Claim 12

A memory control system comprising: a frame buffer memory having a first buffer portion and a second buffer portion; a control logic connected to receive and communicate a control signal comprising instruction and data segments; a read circuit connected between said control logic and said memory for reading from specific addresses specified by said control logic and returning the contents of said addresses to said control logic; a write circuit connected between said control logic and said memory for writing to or clearing specific addresses or groups of addresses in said memory according to said control logic; a suspend circuit connected to disable said write circuit when a suspend-until-frame-blank command is received by said control logic; wherein said control logic is connected to said write circuit to clear a specific said buffer portion and re-enable said write circuit when a frame-blank command is received.

Claim 13

The system of claim 10, wherein said first and second buffer portions comprise distinct address ranges of said memory.

Claim 14

The system of claim 10, wherein said each corresponding location in said first and second buffer portions comprise first and second pixel halves respectively.

Claim 15

The system of claim 10, wherein said memory further comprises a local buffer, said local buffer being operated independently of said first and second buffer portions.

Claim 16

The system of claim 10, wherein said memory comprises VRAM.

Claim 17

The system of claim 10, wherein said data is displayed from said second buffer portion when said first buffer portion is being written.

Claim 18

A pipelined graphics system comprising: a data bus; a rendering circuit connected to said data bus; a frame buffer memory having a first buffer portion and a second buffer portion; a control logic connected to said data bus to receive and communicate a control signal comprising instruction and data segments; a read circuit connected between said data bus and said memory for reading from specific addresses specified by said control logic and returning the contents of said addresses to said control logic; a write circuit connected between said data bus and said memory for writing to or clearing specific addresses or groups of addresses in said memory according to said control logic; a suspend circuit connected to disable said write circuit when a suspend-until-frame-blank command is received by said control logic; and a display circuit for displaying some portion of the contents of said memory; wherein when said write circuit is disabled, all other circuits continue to operate; wherein said control logic is connected to said write circuit to re-enable said write circuit when a frame-blank command is received.

Claim 19

A pipelined graphics system comprising: a data bus; a rendering circuit connected to said data bus; a frame buffer memory having a first buffer portion and a second buffer portion; a control logic connected to said data bus to receive and communicate a control signal comprising instruction and data segments; a read circuit connected between said data bus and said memory for reading from specific addresses specified by said control logic and returning the contents of said addresses to said control logic; a write circuit connected between said data bus and said memory for writing to or clearing specific addresses or groups of addresses in said memory according to said control logic; a suspend circuit connected to disable said write circuit when a suspend-until-frame-blank command is received by said control logic; and a display circuit for displaying some portion of the contents of said memory; wherein when said write circuit is disabled, all other circuits continue to operate; wherein said control logic is connected to said write circuit to re-enable said write circuit when a frame-blank command is received.

Claim 20

The system of claim 16, wherein said frame-blank command is generated by said display circuit when it is ready to display a new set of data.

Claim 21

The system of claim 16, wherein said read circuit is connected to be disabled when said write circuit is disabled.

Claim 22

The system of claim 16, wherein when said frame-blank command is received, a specific said buffer portion is cleared before said write circuit is re-enabled.

Claim 23

The system of claim 16, wherein said read circuit is suspended when said write circuit is suspended.

Claim 24

The system of claim 16, wherein when said write circuit is suspended, said rendering circuit is also suspended.

Claim 25

A graphics processing subsystem, comprising: an input buffer; a rasterizer, connected to read messages from said input buffer and to generate a sequence of pixel locations accordingly; one or more differential data analyzers, operatively connected to receive messages from said rasterizer, and connected to provide a sequence of incrementally changing parameter values for sequences of pixel locations defined by messages received from said rasterizer; a plurality of additional processing units, operatively connected in series in a pipeline relationship, and jointly operatively connected to receive messages from said differential data analyzers; plural ones of said additional processing units each having customized hardware which is different from one another and from said differential data analyzers; said processing units being mutually interconnected in a pipeline relationship, such that individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units; at least one framebuffer memory connected to at least one of said processing unit; a control logic connected to disable write access to said memory when a suspend-until-frame-blank command is received; and wherein a control logic is connected to a write circuit of said memory to re-enable write access to said memory when a frame-blank command is received; and whereby said plural processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture.

Claim 26

A graphics processing subsystem, comprising: an input buffer; a rasterizer, connected to read messages from said input buffer and to generate a sequence of pixel locations accordingly; one or more differential data analyzers, operatively connected to receive messages from said rasterizer, and connected to provide a sequence of incrementally changing parameter values for sequences of pixel locations defined by messages received from said rasterizer; a plurality of additional processing units, operatively connected in series in a pipeline relationship, and jointly operatively connected to receive messages from said differential data analyzers; plural ones of said additional processing units each having customized hardware which is different from one another and from said differential data analyzers; said processing units being mutually interconnected in a pipeline relationship, such that individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units; at least one framebuffer memory connected to at least one of said processing unit; a control logic connected to disable write access to said memory when a suspend-until-frame-blank command is received; and wherein a control logic is connected to a write circuit of said memory to re-enable write access to said memory when a frame-blank command is received; and whereby said plural processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture.

Claim 27

The graphics processing subsystem of claim 22, wherein said parameter is a color value.

Claim 28

The graphics processing subsystem of claim 22, wherein said control logic is connected to said write circuit to clear said memory when said frame-blank command is received and before re-enabling write access to said memory.

Claim 29

The graphics processing subsystem of claim 22, wherein said parameter is a depth value.

Claim 30

The graphics processing subsystem of claim 22, wherein said processing units include a texturing unit.

Claim 31

The graphics processing subsystem of claim 22, wherein said processing units include a memory access unit which reads and writes a local buffer memory.

Claim 32

The graphics processing subsystem of claim 22, wherein at least some ones of said processing units include internally paralleled data paths.

Claim 33

The graphics processing subsystem of claim 22, wherein said rasterizer and said differential data analyzers and all of said additional processing units are integrated into a single integrated circuit.

Claim 34

The graphics processing subsystem of claim 22, wherein said rasterizer generates step messages which are passed through all of said processors.