Thresholding support in performance monitoring

Claim 1

A thresholding mechanism for a performance monitor system in a data processing system comprising: a memory hierarchy including at least one level of cache memory and a main memory for processing a memory request signal and outputting a data completion signal when a memory request signal has been processed; a cycle counter activated by the memory request signal to said memory hierarchy and deactivated by the data completion signal from said memory hierarchy; a clock coupled to the cycle counter, said clock incrementing the cycle counter with each clock cycle after the cycle counter is activated; a monitor mode control register storing a threshold value, the threshold value being variable and software settable; a thresholder connected to said cycle counter to receive an output count value when the cycle counter is deactivated by a data completion signal, said thresholder comparing the threshold value stored in said monitor mode control register with the output count value from the cycle counter, said thresholder generating an output when the count value exceeds the threshold value; an event counter incremented by the output from said thresholder; and output means connected to said event counter for generating an output for performance analysis, said output means accumulating counts of memory accesses for said at least one level of cache and said main memory that exceed decreasing threshold values set in said monitor mode control register and generating a histogram of access time distributions of memory requests for each of said one level of cache and said main memory.

Claim 7

A method of determining a memory access distribution as a function of elapsed clock cycles, the method comprising the steps of: receiving a memory request signal in a memory hierarchy including at least one level of cache memory and a main memory; generating a data completion signal when a memory request signal has been processed by said memory hierarchy; activating a cycle counter upon receiving the memory request signal; incrementing the cycle counter with each clock cycle of a clock while the cycle counter is activated; storing a threshold value in a monitor mode control register; setting variable and decreasing threshold values in said monitor mode control register; deactivating said cycle counter when a data completion signal is received from said memory hierarchy; comparing a count value accumulated by the cycle counter to the threshold value stored in said monitor mode control register when the cycle counter is deactivated by a data completion signal; incrementing an event counter when the count value accumulated by the cycle counter is greater than said threshold value; accumulating counts from said event counter of memory accesses for said at least one level of cache and main memory that exceed decreasing threshold values set in said monitor mode control register; and generating an output for performance analysis, said output including a histogram of access time distributions of memory requests for each of said one level of cache and said main memory.

Claim 8

A method of determining a memory access distribution as a function of elapsed clock cycles, the method comprising the steps of: receiving a memory request signal in a memory hierarchy including at least one level of cache memory and a main memory; generating a data completion signal when a memory request signal has been processed by said memory hierarchy; activating a cycle counter upon receiving the memory request signal; incrementing the cycle counter with each clock cycle of a clock while the cycle counter is activated; storing a threshold value in a monitor mode control register; setting variable and decreasing threshold values in said monitor mode control register; deactivating said cycle counter when a data completion signal is received from said memory hierarchy; comparing a count value accumulated by the cycle counter to the threshold value stored in said monitor mode control register when the cycle counter is deactivated by a data completion signal; incrementing an event counter when the count value accumulated by the cycle counter is greater than said threshold value; accumulating counts from said event counter of memory accesses for said at least one level of cache and main memory that exceed decreasing threshold values set in said monitor mode control register; and generating an output for performance analysis, said output including a histogram of access time distributions of memory requests for each of said one level of cache and said main memory.