Cryptographic system for wireless communications

Claim 2

A base station in a spectrum wireless communications system, comprising: an RF antenna; a reverse channel that receives and processes a signal from a wireless terminal; and a forward channel that transmits an input signal from a mobile switching center to a wireless terminal, said forward channel circuit comprising: a channel coder responsive to said mobile switching center that error correction codes said input signal, a bit interleaver responsive to said channel coder that rearranges the order of the bits in the input signal so as to minimize the effect of error bursts, an encryptor responsive to said channel coder that encrypts said input signal, said encryptor including a nonlinear scrambler for generating a key signal comprising a sequence of bits that have a nonlinear relationship to a private long code mask, and circuitry responsive to said channel coder, said bit interleaver and said encryptor and coupled to said antenna for modulating and transmitting said input signal.

Claim 3

The base station of claim 1, wherein said encryptor comprises: a long code generator that creates a long code sequence from a long code mask; a nonlinear scrambler responsive to said long code generator that creates a key signal that is a nonlinear function of the bits of the long code mask; and a circuit responsive to said bit interleaver and said nonlinear scrambler that encrypts said input signal.

Claim 4

The base station of claim 2, wherein said non-linear scrambler comprises: a shift register having a first predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code register; a first logic circuit coupled to said shift register so as to access the contents of selected cells, said first logic circuit having an output; a second logic circuit having first and second inputs and an output, said first input coupled to said long code generator, said second input coupled to said output of said first logic circuit, and said output coupled to said input of said shift register so as to provide a feedback loop for said nonlinear scrambler, said output of said second logic circuit also comprising the output of said nonlinear scrambler.

Claim 5

The base station of claim 3, wherein said second logic circuit comprises an Exclusive-OR gate.

Claim 6

The base station of claim 2, wherein said nonlinear scrambler includes a feedback loop.

Claim 7

The base station of claim 2 wherein said nonlinear scrambler comprises a feedback loop such that an output bit of said nonlinear scrambler is used to create a subsequent output bit.

Claim 8

The base station of claim 2, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a combinational logic circuit coupled to tap the contents of selected cells of said shift register so as to provide an output for said nonlinear scrambler.

Claim 9

The base station of claim 7, wherein said combinational logic circuit comprises an AND-gate having at least two inputs coupled to selected cells of said shift register.

Claim 10

The base station of claim 2, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a multiplexer having a predetermined number of data inputs and a predetermined number of selector inputs, said selector inputs coupled to a first set of selected cells of said shift register and said data inputs coupled to a second selected set of cells of said shift register such that the first set of cells selects among the second set of cells to provide an output from said multiplexer.

Claim 11

The base station of claim 9, wherein said first and second sets of cells are mutually exclusive.

Claim 12

The base station of claim 9, wherein said first and second sets of cells share a predetermined number of cells.

Claim 13

The base station of claim 2, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; a data encryption standard circuit having a predetermined number of inputs coupled to selected cells of said shift register for using a key signal to create an encrypted output bit for each input; and a register having a predetermined number of cells, each cell coupled to receive a bit output by said data encryption standard circuit, a selected cell of said register providing the output of said nonlinear scrambling register.

Claim 14

The base station of claim 2, wherein said nonlinear scrambler comprises: a feedback circuit responsive to said long code generator, said feedback circuit including a shift register; and a combinational logic circuit coupled to tap selected cells of said shift register so as to generate an output for said nonlinear scrambler.

Claim 15

An encryptor for encrypting an input signal in a forward channel of a spread spectrum wireless communication system, said encryptor comprising: a long code generator that creams a long code sequence from a long code mask; a nonlinear scrambler responsive to said long code generator that creates a key signal that is a nonlinear function of the bits of the long code mask; and a combinational logic circuit that encrypts said input signal with said key signal.

Claim 16

An encryptor for encrypting an input signal in a forward channel of a spread spectrum wireless communication system, said encryptor comprising: a long code generator that creams a long code sequence from a long code mask; a nonlinear scrambler responsive to said long code generator that creates a key signal that is a nonlinear function of the bits of the long code mask; and a combinational logic circuit that encrypts said input signal with said key signal.

Claim 17

The encryptor of claim 14, wherein said non-linear scrambling circuit comprises: a shift register having a first predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code register; a first logic circuit coupled to said shift register so as to access the contents of predetermined cells, said first logic circuit having an output; a second logic circuit having first and second inputs and an output, said first input coupled to said long code generator, said second input coupled to said output of said first logic circuit, and said output coupled to said input of said shift register so as to provide a feedback loop for said nonlinear scrambler, said output of said second logic circuit also comprising the output of said nonlinear scrambler.

Claim 18

The encryptor of claim 15, wherein said second logic circuit comprises an Exclusive-OR gate.

Claim 19

The encryptor of claim 14, wherein said nonlinear scrambler comprises a feedback loop such that an output bit of said nonlinear scrambler is used to create a subsequent output bit.

Claim 20

The encryptor of claim 14, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a combinational logic circuit coupled to tap the contents of a predetermined number of said cells of said shift register so as to provide an output of said nonlinear scrambler.

Claim 21

The encryptor of claim 18, wherein said combinational logic circuit comprises an AND-gate having at least two inputs coupled to selected cells of said shift register.

Claim 22

The encryptor of claim 14, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a multiplexer having a predetermined number of data inputs and a predetermined number of selector inputs, said selector inputs coupled to a first set of selected cells of said shift register and said data inputs coupled to a second selected set of cells of said shift register such that the first set of cells selects among the second set of cells to provide an output from said multiplexer.

Claim 23

The base station of claim 20, wherein said first and second sets of cells are mutually exclusive.

Claim 24

The base station of claim 20, wherein said first and second sets of cells share a predetermined number of cells.

Claim 25

The base station of claim 14, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; a data encryption standard circuit having a predetermined number of inputs coupled to selected cells of said shift register for using a key signal to create an encrypted output bit for each input; and a register having a predetermined number of cells, each cell coupled to receive a bit output by said data encryption standard circuit, a selected cell of said register providing the output of said nonlinear scrambling register.

Claim 26

A wireless terminal for a spread spectrum wireless communication system, comprising; an RF antenna; a reverse channel circuit that processes and transmits a signal to a base station; and a forward channel circuit that receives and processes a transmitted signal from a base station, said forward channel circuit comprising: a receiver circuit coupled to said antenna that demodulates said transmitted signal, a decryptor responsive to said receiver circuit that decrypts said transmitted signal, said decryptor including a nonlinear scrambler for generating a key signal comprising a sequence of bits that have a nonlinear relationship to a private long code mask, a bit deinterleaver responsive to said receiver circuit that rearranges the order of the bits in the transmitted signal, a channel decoder responsive to said receiver circuit that utilizes error correction coding of said transmitted signal to provide error correction, a voice decoder responsive to said receiver circuit that generates an output signal from said transmitted signal, and an output device for outputting the transmitted signal.

Claim 27

A wireless terminal for a spread spectrum wireless communication system, comprising; an RF antenna; a reverse channel circuit that processes and transmits a signal to a base station; and a forward channel circuit that receives and processes a transmitted signal from a base station, said forward channel circuit comprising: a receiver circuit coupled to said antenna that demodulates said transmitted signal, a decryptor responsive to said receiver circuit that decrypts said transmitted signal, said decryptor including a nonlinear scrambler for generating a key signal comprising a sequence of bits that have a nonlinear relationship to a private long code mask, a bit deinterleaver responsive to said receiver circuit that rearranges the order of the bits in the transmitted signal, a channel decoder responsive to said receiver circuit that utilizes error correction coding of said transmitted signal to provide error correction, a voice decoder responsive to said receiver circuit that generates an output signal from said transmitted signal, and an output device for outputting the transmitted signal.

Claim 28

The wireless terminal of claim 24, wherein said decryptor comprises: a long code generator that creates a long code sequence from a long code mask; a nonlinear scrambler responsive to said long code generator that creates an key signal that is a nonlinear function of the bits of the long code mask; and a combinational logic circuit responsive to said nonlinear scrambler and said receiver circuit that decrypts said transmitted signal.

Claim 29

The wireless terminal of claim 25, wherein said non-linear scrambling circuit comprises: a shift register having a first predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code register; a first logic circuit coupled to said shift register so as to access the contents of selected cells, said first logic circuit having an output; a second logic circuit having first and second inputs and an output, said first input coupled to said long code generator, said second input coupled to said output of said first logic circuit, and said output coupled to said input of said shift register so as to provide a feedback loop for said nonlinear scrambler, said output of said second logic circuit also comprising the output of said nonlinear scrambler.

Claim 30

The wireless terminal of claim 26, wherein said second logic circuit comprises an Exclusive-OR gate.

Claim 31

The wireless terminal of claim 25, wherein said nonlinear scrambler includes a feedback loop.

Claim 32

The wireless terminal of claim 25 wherein said nonlinear scrambler comprises a feedback loop such that an output bit of said nonlinear scrambler is used to create a subsequent output bit.

Claim 33

The wireless terminal of claim 25, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a combinational logic circuit coupled to tap the contents of selected cells of said shift register so as to provide an output of said nonlinear scrambler.

Claim 34

The wireless terminal of claim 30, wherein said combinational logic circuit comprises an AND-gate having at least two inputs coupled to selected cells of said shift register.

Claim 35

The wireless terminal of claim 25, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a multiplexer having a predetermined number of data inputs and a predetermined number of selector inputs, said selector inputs coupled to a first set of selected cells of said shift register and said data inputs coupled to a second selected set of cells of said shift register such that the first set of cells selects among the second set of cells to provide an output from said multiplexer.

Claim 36

The wireless terminal of claim 32, wherein said first and second sets of cells are mutually exclusive.

Claim 37

The wireless terminal of claim 32, wherein said first and second sets of cells share a predetermined number of cells.

Claim 38

The wireless terminal of claim 25, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; a data encryption standard circuit having a predetermined number of inputs coupled to selected cells of said shift register for using a key signal to create an encrypted output bit for each input; and a register having a predetermined number of cells, each cell coupled to receive a bit output by said data encryption standard circuit, a selected cell of said register providing the output of said nonlinear scrambling register.

Claim 39

The wireless terminal of claim 25, wherein said nonlinear scrambler comprises: a feedback circuit responsive to said long code generator, said feedback circuit including a shift register; and a combinational logic circuit coupled to tap selected cells of said shift register so as to generate an output for said nonlinear scrambler.

Claim 42

The method of claim 37 wherein said step of generating a key signal comprises the steps of: generating a long code sequence from a long code mask in a long code generator; and scrambling said long code sequence in a nonlinear scrambler.

Claim 43

The method of claim 38 wherein said step of scrambling the long code sequence comprises the step of scrambling the long code sequence in a nonlinear scrambler having a feedback loop.

Claim 44

The method of claim 38 wherein said step of scrambling the long code sequence comprises the step of scrambling the long code sequence in a nonlinear scrambler having a shift register coupled to receive the long code sequence and a combinational logic circuit coupled to selected cells of the shift register to generate the output of the nonlinear scrambler.

Claim 45

The method of claim 38 wherein said step of scrambling the long code sequence comprises the steps of: shifting the bits of the long code sequence through a shift register having a predetermined number of cells; and using selected cells of said shift register to select among the cells of the shift register to provide an output of said nonlinear scrambler.

Claim 46

The method of claim 38 wherein said step of scrambling the long code sequence comprises the steps of: shifting the bits of the long code sequence through a shift register having a predetermined number of cells; and encrypting the bits in said shift register with a data encryption standard circuit and a second key signal.

Claim 47

A spread spectrum wireless infrastructure, comprising: a mobile switching center coupled to receive input signals from at least one local office and at least one toll office; a plurality of base stations coupled to said mobile switching center, each base station comprising: an RF antenna; a reverse channel that receives and processes a signal from a wireless terminal; and a forward channel that transmits an input signal from one of said mobile switching centers to a wireless terminal, said forward channel circuit comprising: a channel coder responsive to said mobile switching center that error correction codes said input signal, a bit interleaver responsive to said channel coder that rearranges the order of the bits in the input signal so as to minimize the effect of error bursts, an encryptor responsive to said channel coder that encrypts said input signal, said encryptor including a nonlinear scrambler for generating a key signal comprising a sequence of bits that have a nonlinear relationship to a private long code mask, and circuitry responsive to said channel coder and coupled to said antenna that modulates said input signal.

Claim 48

A spread spectrum wireless infrastructure, comprising: a mobile switching center coupled to receive input signals from at least one local office and at least one toll office; a plurality of base stations coupled to said mobile switching center, each base station comprising: an RF antenna; a reverse channel that receives and processes a signal from a wireless terminal; and a forward channel that transmits an input signal from one of said mobile switching centers to a wireless terminal, said forward channel circuit comprising: a channel coder responsive to said mobile switching center that error correction codes said input signal, a bit interleaver responsive to said channel coder that rearranges the order of the bits in the input signal so as to minimize the effect of error bursts, an encryptor responsive to said channel coder that encrypts said input signal, said encryptor including a nonlinear scrambler for generating a key signal comprising a sequence of bits that have a nonlinear relationship to a private long code mask, and circuitry responsive to said channel coder and coupled to said antenna that modulates said input signal.

Claim 49

The wireless infrastructure of claim 43, wherein said encryptor comprises: a long code generator for creating a long code sequence from a long code mask; a nonlinear scrambler responsive to said long code generator for creating a key signal that is a nonlinear function of the bits of the long code mask; and a combinational logic circuit responsive to said bit interleaver for encrypting said input signal.

Claim 50

The wireless infrastructure of claim 44, wherein said non-linear scrambler comprises: a shift register having a first predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code register; a first logic circuit coupled to said shift register so as to access the contents of selected cells, said first logic circuit having an output; a second logic circuit having first and second inputs and an output, said first input coupled to said long code generator, said second input coupled to said output of said first logic circuit, and said output coupled to said input of said shift register so as to provide a feedback loop for said nonlinear scrambler, said output of said second logic circuit also comprising the output of said nonlinear scrambler.

Claim 51

The wireless infrastructure of claim 45, wherein said second logic circuit comprises an Exclusive-OR gate.

Claim 52

The wireless infrastructure of claim 44, wherein said nonlinear scrambler includes a feedback loop.

Claim 53

The wireless infrastructure of claim 44 wherein said nonlinear scrambler comprises a feedback loop such that an output bit of said nonlinear scrambler is used to create a subsequent output bit.

Claim 54

The wireless infrastructure of claim 44, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a combinational logic circuit coupled to tap the contents of selected cells of said shift register so as to provide an output of said nonlinear scrambler.

Claim 55

The wireless infrastructure of claim 49, wherein said combinational logic circuit comprises an AND-gate having at least two inputs coupled to selected cells of said shift register.

Claim 56

The wireless infrastructure of claim 44, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; and a multiplexer having a predetermined number of data inputs and a predetermined number of selector inputs, said selector inputs coupled to a first set of selected cells of said shift register and said data inputs coupled to a second selected set of cells of said shift register such that the first set of cells selects among the second set of cells to provide an output from said multiplexer.

Claim 57

The wireless infrastructure of claim 51, wherein said first and second sets of cells are mutually exclusive.

Claim 58

The wireless infrastructure of claim 51, wherein said first and second sets of cells share a predetermined number of cells.

Claim 59

The wireless infrastructure of claim 44, wherein said nonlinear scrambler comprises: a shift register having a predetermined number of cells, said shift register having an input to receive a stream of input bits from said long code generator; a data encryption standard circuit having a predetermined number of inputs coupled to selected cells of said shift register for using a key signal to create an encrypted output bit for each input; and a register having a predetermined number of cells, each cell coupled to receive a bit output by said data encryption standard circuit, a selected cell of said register providing the output of said nonlinear scrambling register.

Claim 60

The wireless infrastructure of claim 44, wherein said nonlinear scrambler comprises: a feedback circuit responsive to said long code generator, said feedback circuit including a shift register; and a combinational logic circuit coupled to tap selected cells of said shift register so as to generate an output for said nonlinear scrambler.