Nonvolatile semiconductor memory device and method of fabrication of the same

Claim 2

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a transistor formed on said semiconductor substrate, including a gate structure formed on a region of the surface of said substrate, a pair of mutually-isolated impurities diffusion layers of first conduction type formed on the two sides of said gate structure on the surface of said semiconductor substrate, and a second impurities diffusion layer of second conduction type different from the first conduction type, formed in such a manner as to cover the substrate's side of at least one of said first impurities diffusion layers, said second impurities diffusion layer having a terminal section reaching a region of the surface of said semiconductor substrate, said second impurities diffusion layer forming the channel region of said transistor; and a conduction layer electrically connected to said second impurities diffusion layer and formed accessibly externally.

Claim 3

A nonvolatile semiconductor memory device according to claim 1, wherein said second impurities diffusion layer has an extension to the surface of said semiconductor substrate, and said conduction layer is formed on an interlayer insulating film formed on said semiconductor substrate in such a manner as to cover said transistor, said conduction layer being connected to said extension of said second impurities diffusion layer through a contact hole formed in said interlayer insulating film.

Claim 4

A nonvolatile semiconductor memory device according to claim 2, further comprising at least one elongated element-isolating field oxide film formed on said semiconductor substrate in order to define at least two electrically-isolated element-activating regions on said semiconductor substrate, wherein said transistor is formed on one of said two element-activating regions, and the extension of said second impurities diffusion layer passes under said field oxide film and extends to the other of said two element-activating regions.

Claim 5

A nonvolatile semiconductor memory device according to claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type.

Claim 6

A nonvolatile semiconductor memory device according to claim 2, further comprising at least one elongated element-isolation electrode formed on the semiconductor substrate for defining element activating regions electrically isolated from each other in the semiconductor substrate at both sides of the element-isolation electrode, and wherein said transistor is formed in one of said element activating regions and said extension of said second impurity diffusion layer extends beneath the element-isolation electrode into the other element activating region.

Claim 7

A nonvolatile semiconductor memory device according to claim 1, wherein said semiconductor substrate is the first conduction type.

Claim 8

A nonvolatile semiconductor memory device comprising: a semiconductor substrate of first conduction type; at least a memory cell transistor formed on said semiconductor substrate, including a stacked gate structure having a floating gate formed on a predetermined region of the surface of said semiconductor substrate through a first insulating film and a control gate formed on said floating gate through a second insulating film, a pair of mutually-isolated first impurities diffusion layers of first conduction type formed on the two sides of said gate structure on the surface of said semiconductor substrate and having a resistance lower than said semiconductor substrate, and a second impurities diffusion layer of second conduction type different from said first conduction type, said second impurities diffusion layer being formed in such a manner as to surround one of said two first impurities diffusion layers in said semiconductor substrate and having a terminal section reaching a predetermined region on the surface of said semiconductor substrate thereby to form the channel region of said transistor; an extension of said second impurities diffusion layer extending in said semiconductor substrate; and a conduction layer electrically connected to said extension and accessible externally.

Claim 9

A nonvolatile semiconductor memory device comprising: a semiconductor substrate of first conduction type; at least a memory cell transistor formed on said semiconductor substrate, including a stacked gate structure having a floating gate formed on a predetermined region of the surface of said semiconductor substrate through a first insulating film and a control gate formed on said floating gate through a second insulating film, a pair of mutually-isolated first impurities diffusion layers of first conduction type formed on the two sides of said gate structure on the surface of said semiconductor substrate and having a resistance lower than said semiconductor substrate, and a second impurities diffusion layer of second conduction type different from said first conduction type, said second impurities diffusion layer being formed in such a manner as to surround one of said two first impurities diffusion layers in said semiconductor substrate and having a terminal section reaching a predetermined region on the surface of said semiconductor substrate thereby to form the channel region of said transistor; an extension of said second impurities diffusion layer extending in said semiconductor substrate; and a conduction layer electrically connected to said extension and accessible externally.

Claim 10

A nonvolatile semiconductor memory device according to claim 7, further comprising at least one elongated element-isolation electrode formed on the semiconductor substrate for defining element activating regions electrically isolated from each other in the semiconductor substrate at both sides of the element-isolation electrode, and wherein said transistor is formed in one of said element activating regions and said extension of said second impurity diffusion layer extends beneath the element-isolation electrode into the other element activating region.

Claim 11

A nonvolatile semiconductor memory device according to claim 7, wherein said first conductivity type is N-type and said second conductivity type is P-type.

Claim 12

A nonvolatile semiconductor memory device according to claim 7, wherein said conduction layer is formed on an interlayer insulating layer formed on said semiconductor substrate in such a manner as to cover said memory transistor, said conduction layer being connected to said extension of said second impurities diffusion layer through a contact hole formed in said interlayer insulating film.

Claim 13

A nonvolatile semiconductor memory device according to claim 7, further comprising at least an elongated element-isolating field oxide film formed on said semiconductor substrate in order to define at least two electrically-isolated element-activating regions on said semiconductor substrate, said transistor being formed on one of said two element-activating regions, the extension of said second impurities diffusion layer passing under said field oxide film and extending to the other of the two element-activating regions.

Claim 14

A nonvolatile semiconductor memory device comprising: a first semiconductor substrate of first conduction type; at least a memory cell transistor formed on said semiconductor substrate, each including a gate electrode formed on a predetermined region of the surface of said semiconductor substrate through an insulating film, a pair of first impurities diffusion layers of first conduction type formed in isolated relation to each other on the two sides of said gate electrode on the surface of said semiconductor substrate and having a resistance lower than said semiconductor substrate, and a second impurities diffusion layer of second conduction type different from said first conduction type, formed in such a manner as to surround one of said first impurities diffusion layers in said semiconductor substrate and having a terminal section reaching a predetermined region of the surface of said semiconductor substrate, thereby forming the channel region of said transistor; an extension of said second impurities diffusion layer extending in said semiconductor substrate; and a conduction layer electrically connected to said extension and formed accessible externally.

Claim 15

A nonvolatile semiconductor memory device comprising: a first semiconductor substrate of first conduction type; at least a memory cell transistor formed on said semiconductor substrate, each including a gate electrode formed on a predetermined region of the surface of said semiconductor substrate through an insulating film, a pair of first impurities diffusion layers of first conduction type formed in isolated relation to each other on the two sides of said gate electrode on the surface of said semiconductor substrate and having a resistance lower than said semiconductor substrate, and a second impurities diffusion layer of second conduction type different from said first conduction type, formed in such a manner as to surround one of said first impurities diffusion layers in said semiconductor substrate and having a terminal section reaching a predetermined region of the surface of said semiconductor substrate, thereby forming the channel region of said transistor; an extension of said second impurities diffusion layer extending in said semiconductor substrate; and a conduction layer electrically connected to said extension and formed accessible externally.

Claim 16

A nonvolatile semiconductor memory device according to claim 12, further comprising at least one elongated element-isolation electrode formed on the semiconductor substrate for defining element activating regions electrically isolated from each other in the semiconductor substrate at both sides of the element-isolation electrode, and wherein said transistor is formed in one of said element activating regions and said extension of said second impurity diffusion layer extends beneath the element-isolation electrode into the other element activating region.

Claim 17

A nonvolatile semiconductor memory device according to claim 12, wherein said conduction layer is formed on an interlayer insulating film formed on said semiconductor substrate in such a manner as to cover said memory transistor, said conduction layer being connected to said extension of said second impurities diffusion layer through a contact hole formed in said interlayer insulating film.

Claim 18

A nonvolatile semiconductor memory device according to claim 12, further comprising at least one elongated element-isolating field oxide film formed on said semiconductor substrate in order to define at least two electrically-isolated element-activating regions on said semiconductor substrate, at least one of said transistors being formed on one of said two element-activating regions, the extension of said second impurities diffusion layer passing under said field oxide film and extending to the other of said two element-activating regions.