US5724368A
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Cyclical redundancy check method and apparatus
Assignee: Cirrus Logic Inc
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Filing: 1996-10-02
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Granted: 1998-03-03
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Expires: 2016-10-02
Abstract
Abstract A one stage CRC generation system (400) and a two stage CRC generation system (600) feature a CRC generator/checker (700) which outputs a programmable number of CRC bytes. The CRC generation/checker (700) comprises a segmenting circuit (710) for segmenting an input stream of user data into a plurality m of sub-streams!; a circuit (712) which forms a linear combination of the plurality m of sub-streams and operates upon the linear combination in order to generate CRC bytes; and, a checker circuit (714) for comparing the generated CRC bytes with previously generated CRC bytes. The two stage system (600) includes a first CRC generator/checker (601); a memory (602) which receives both the user data and K 1 number of primary CRC bytes generated by first CRC generator/checker (601); and, a second CRC generator/checker (603) which uses the primary CRC bytes and K 1 number of its own generated verification CRC bytes to check the user data after retrieval from memory (602) and prior to encoding. In addition, second CRC generator/checker (603) can optionally apply K 2 -K 1 number of its verification CRC bytes to encoder (604) for use as secondary CRC bytes. The number of CRC bytes K 1 and K 2 actually outputted by the respective CRC generator/checkers (601,603) is programmable.
Inventors
- 👤 Christopher P. Zook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:49
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1004; G06F11/1008; G06F11/1068; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833; H03M13/35
Claims Analysis
Total Claims: 81
Claim 1
Independent Claim
77 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the interleaving circuit divides the input stream into three interleaves.
Claim 2
Dependent Claim
77 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the interleaving circuit divides the input stream into three interleaves.
Claim 3
Dependent Claim
84 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the interleaving circuit includes a multiplier for multiplying at least one of the interleaves by a constant.
Claim 4
Dependent Claim
84 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the interleaving circuit includes a multiplier for multiplying at least one of the interleaves by a constant.
Claim 5
Dependent Claim
20 words
The apparatus of claim 2, wherein the multiplier is chosen so that a linear combination of certain bytes is non-zero.
Claim 6
Dependent Claim
16 words
The apparatus of claim 3, wherein the constant is a power of a field element α.
Claim 7
Dependent Claim
49 words
The apparatus of claim 4, wherein there are three interleaves, wherein each byte of one interleave is multiplied by a constant M 1 , each byte of another interleave is multiplied by a constant M 2 , and wherein M 1 =α 25 and M 2 =α 112 .
Claim 8
Dependent Claim
112 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information comprises k number of sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves.
Claim 9
Dependent Claim
112 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information comprises k number of sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves.
Claim 10
Dependent Claim
125 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein each interleave forms at least part of a data polynomial, and wherein the circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information comprises k number of divider sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves.
Claim 11
Dependent Claim
125 words
An error correction generator comprising: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein each interleave forms at least part of a data polynomial, and wherein the circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information comprises k number of divider sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves.
Claim 12
Dependent Claim
26 words
The apparatus of claim 7, wherein each divider sub-circuit divides the data polynomial by a divisor which is related to a root of an ECC polynomial.
Claim 13
Dependent Claim
74 words
An error correction generator comprising: means for dividing an input stream of data into a plurality of interleaves; means for forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the dividing means divides the input stream into three interleaves.
Claim 14
Dependent Claim
74 words
An error correction generator comprising: means for dividing an input stream of data into a plurality of interleaves; means for forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the dividing means divides the input stream into three interleaves.
Claim 15
Dependent Claim
77 words
An error correction generator comprising: means for dividing an input stream of data into a plurality of interleaves; means for forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the dividing means multiplies at least one of the interleaves by a constant.
Claim 16
Dependent Claim
77 words
An error correction generator comprising: means for dividing an input stream of data into a plurality of interleaves; means for forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein the dividing means multiplies at least one of the interleaves by a constant.
Claim 17
Dependent Claim
20 words
The apparatus of claim 10, wherein the constant is chosen so that a linear combination of certain bytes is non-zero.
Claim 18
Dependent Claim
16 words
The apparatus of claim 11, wherein the constant is a power of a field element α.
Claim 19
Dependent Claim
51 words
The apparatus of claim 12, wherein there are three interleaves, each interleave constituting a byte of data, and wherein one interleave is multiplied by a constant M 1 and another interleave is multiplied by a constant M 2 , and wherein M 1 =α 25 and M 2 =α 112 .
Claim 20
Dependent Claim
121 words
An error correction generator comprising: means for dividing an input stream of data into a plurality of interleaves; means for forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein each interleave forms at least part of a data polynomial, and the means for forming a linear combination of the plurality of interleaves and for operating upon the linear combination in order to generate the CRC information comprises k number of dividers for generating k bytes of CRC information with respect to the linear combination of interleaves.
Claim 21
Dependent Claim
121 words
An error correction generator comprising: means for dividing an input stream of data into a plurality of interleaves; means for forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and an error correction circuit which generates error correction (ECC) information using the input stream and the CRC information; wherein each interleave forms at least part of a data polynomial, and the means for forming a linear combination of the plurality of interleaves and for operating upon the linear combination in order to generate the CRC information comprises k number of dividers for generating k bytes of CRC information with respect to the linear combination of interleaves.
Claim 22
Dependent Claim
25 words
The apparatus of claim 14, wherein each divider divides the data polynomial by a divisor which is related to a root of an ECC polynomial.
Claim 23
Dependent Claim
52 words
The apparatus of claim 14, wherein the means for forming a linear combination of the plurality of interleaves and for operating upon the linear combination in order to generate the CRC information outputs K 1 number of bytes of CRC information, K 1 being a constant less than or equal to k.
Claim 24
Dependent Claim
10 words
The apparatus of claim 16, wherein K 1 is programmable.
Claim 25
Dependent Claim
66 words
An error correction method comprising: dividing an input stream of data into a plurality of interleaves; and, forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and then using the input stream and the CRC information to generate error correction (ECC) information; wherein the input stream is divided into three interleaves.
Claim 26
Dependent Claim
66 words
An error correction method comprising: dividing an input stream of data into a plurality of interleaves; and, forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and then using the input stream and the CRC information to generate error correction (ECC) information; wherein the input stream is divided into three interleaves.
Claim 27
Dependent Claim
67 words
An error correction method comprising: dividing an input stream of data into a plurality of interleaves; and, forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and then using the input stream and the CRC information to generate error correction (ECC) information; multiplying at least one of the interleaves by a constant.
Claim 28
Dependent Claim
67 words
An error correction method comprising: dividing an input stream of data into a plurality of interleaves; and, forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate cyclical redundancy check (CRC) information; and then using the input stream and the CRC information to generate error correction (ECC) information; multiplying at least one of the interleaves by a constant.
Claim 29
Dependent Claim
20 words
The method of claim 19, wherein the constant is chosen so that the linear combinations of the interleaves are non-zero.
Claim 30
Dependent Claim
16 words
The method of claim 20, wherein the constant is a power of a field element α.
Claim 31
Dependent Claim
49 words
The method of claim 21, wherein there are three interleaves, wherein each byte of one interleave is multiplied by a constant M 1 and each byte of another interleaved is multiplied by a constant M 2 , and wherein M 1 =α 25 and M 2 =α 112 .
Claim 32
Dependent Claim
119 words
A cyclical redundancy check (CRC) method which generates CRC information for error checking purposes, the method comprising: dividing an input stream of data into a plurality of interleaves; forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the CRC information by applying the plurality of interleaves to k number of sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves, the sub-circuits being numbered from a first sub-circuit to a k th sub-circuit; and storing CRC information in a register of each sub-circuit and shifting CRC information stored in the register of the k th sub-circuit to the register of the first sub-circuit.
Claim 33
Dependent Claim
119 words
A cyclical redundancy check (CRC) method which generates CRC information for error checking purposes, the method comprising: dividing an input stream of data into a plurality of interleaves; forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the CRC information by applying the plurality of interleaves to k number of sub-circuits for generating k bytes of CRC information with respect to the linear combination of interleaves, the sub-circuits being numbered from a first sub-circuit to a k th sub-circuit; and storing CRC information in a register of each sub-circuit and shifting CRC information stored in the register of the k th sub-circuit to the register of the first sub-circuit.
Claim 34
Dependent Claim
27 words
The method of claim 23, wherein for sub-circuit j, the linear combination applied thereto is divided by a factor related to a root of an ECC polynomial.
Claim 35
Dependent Claim
36 words
The method of claim 23, further comprising storing CRC information in a register of each sub-circuit and shifting CRC information stored in the register of the k th sub-circuit to the register of the first sub-circuit.
Claim 36
Dependent Claim
30 words
The method of claim 23, further comprising comparing a CRC value inputted to a comparison one of the sub-circuits to CRC information stored in the register of the comparison sub-circuit.
Claim 37
Dependent Claim
116 words
An error correction method comprising: (a) performing an error correction operation on an input stream of data obtained from a communications channel to obtain a corrected input stream including corrected CRC information, then (b) dividing data in the corrected input stream of data into a plurality of interleaves; (c) forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the cyclical redundancy check (CRC) information; (d) comparing the generated CRC information with the corrected CRC information obtained from the communication channel; and (e) producing an error signal when a discrepancy is detected between the generated CRC information and the corrected CRC information obtained from the communication channel.
Claim 38
Dependent Claim
116 words
An error correction method comprising: (a) performing an error correction operation on an input stream of data obtained from a communications channel to obtain a corrected input stream including corrected CRC information, then (b) dividing data in the corrected input stream of data into a plurality of interleaves; (c) forming a linear combination of the plurality of interleaves and operating upon the linear combination in order to generate the cyclical redundancy check (CRC) information; (d) comparing the generated CRC information with the corrected CRC information obtained from the communication channel; and (e) producing an error signal when a discrepancy is detected between the generated CRC information and the corrected CRC information obtained from the communication channel.
Claim 39
Dependent Claim
71 words
The method of claim 27, wherein the CRC information generated in step (b) constitutes K 1 number of bytes stored in registers j=1, . . . k, wherein the decoded CRC information constitutes K 1 number of decoded CRC bytes j=1, . . . k sequentially applied to a comparator, and wherein the comparison step comprises using the comparitor to compare the contents of register j with decoded CRC byte j.
Claim 40
Dependent Claim
12 words
The method of claim 28, wherein K 1 is a programmable integer.
Claim 41
Dependent Claim
38 words
The method of claim 27, further comprising sequentially shifting K 1 -1 number of values stored in registers j=2, . . . k into a selected one of the registers for comparison with a corresponding decoded CRC byte.
Claim 42
Dependent Claim
12 words
The method of claim 30, wherein K 1 is a programmable integer.
Claim 43
Dependent Claim
124 words
An error correction system comprising: a host port connected to a host device; a first cyclical redundancy check (CRC) generator connected to the host port for generating primary CRC information based on input data received from the host device; a semiconductor memory for storing therein input data received from the host device and the primary CRC information generated with respect thereto by the first CRC generator; a second cyclical redundancy check (CRC) generator connected to the semiconductor memory for generating verification CRC information for checking data retrieved from the semiconductor memory; an encoder connected to form encoded information for storage on a peripheral storage device, the encoded information being formed by utilizing the data retrieved from the semiconductor memory including the primary CRC information.
Claim 44
Dependent Claim
124 words
An error correction system comprising: a host port connected to a host device; a first cyclical redundancy check (CRC) generator connected to the host port for generating primary CRC information based on input data received from the host device; a semiconductor memory for storing therein input data received from the host device and the primary CRC information generated with respect thereto by the first CRC generator; a second cyclical redundancy check (CRC) generator connected to the semiconductor memory for generating verification CRC information for checking data retrieved from the semiconductor memory; an encoder connected to form encoded information for storage on a peripheral storage device, the encoded information being formed by utilizing the data retrieved from the semiconductor memory including the primary CRC information.
Claim 45
Dependent Claim
34 words
The apparatus of claim 32, wherein the second CRC generator compares the primary CRC information and the verification CRC information generated by the second CRC generator to determine errors attributable to the semiconductor memory.
Claim 46
Dependent Claim
47 words
The apparatus of claim 32, wherein the second CRC generator also generates secondary CRC information based on data obtained from the semiconductor memory; and wherein the encoder is also connected to the second CRC generator and also utilizes the secondary CRC information to form the encoded information.
Claim 47
Dependent Claim
112 words
The apparatus of claim 32, further comprising: a utilization port connected to a utilization channel; a decoder connected to receive input data at the utilization port and to decode the input data into decoded input data including decoded CRC information, the decoder being connected to apply the decoded input data including the decoded CRC information to the second CRC generator and to the semiconductor memory, the second CRC generator validating decoded CRC information included in the decoded input data, and wherein the first CRC generator is connected to receive decoded input data including the decoded CRC information stored in the semiconductor memory for validating decoded CRC information received from the semiconductor memory.
Claim 48
Dependent Claim
51 words
The apparatus of claim 32, wherein the first CRC generator comprises: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information.
Claim 49
Dependent Claim
51 words
The apparatus of claim 32, wherein the second CRC generator comprises: an interleaving circuit for dividing an input stream of data into a plurality of interleaves; a circuit which forms a linear combination of the plurality of interleaves and operates upon the linear combination in order to generate the CRC information.
Claim 50
Dependent Claim
107 words
A cyclical redundancy check (CRC) method comprising: using a first cyclical redundancy check (CRC) generator to generate primary CRC information based on input data received from a host device; storing in a semiconductor memory the input data received from the host device and the primary CRC information generated with respect thereto by the first CRC generator; using a second cyclical redundancy check (CRC) generator connected to the semiconductor memory for generating verification CRC information with respect to data retrieved from the semiconductor memory; forming encoded information by utilizing the data retrieved from the semiconductor memory including the primary CRC information for storage on a peripheral storage device.
Claim 51
Dependent Claim
107 words
A cyclical redundancy check (CRC) method comprising: using a first cyclical redundancy check (CRC) generator to generate primary CRC information based on input data received from a host device; storing in a semiconductor memory the input data received from the host device and the primary CRC information generated with respect thereto by the first CRC generator; using a second cyclical redundancy check (CRC) generator connected to the semiconductor memory for generating verification CRC information with respect to data retrieved from the semiconductor memory; forming encoded information by utilizing the data retrieved from the semiconductor memory including the primary CRC information for storage on a peripheral storage device.
Claim 52
Dependent Claim
36 words
The method of claim 38, further comprising using the second CRC generator to compare the primary CRC information and verification CRC information generated by the second CRC generator to determine errors attributable to the semiconductor memory.
Claim 53
Dependent Claim
110 words
The method of claim 38, further comprising: decoding input data received from a utilization channel into decoded input data including decoded CRC information; applying the decoded input data including the decoded CRC information to the second CRC generator and to the semiconductor memory; storing the decoded input data including the decoded CRC information in the semiconductor memory; using the second CRC generator to validate the decoded CRC information included in the decoded input data; applying the decoded input data including the decoded CRC information from the semiconductor memory to the first CRC generator; and using the first CRC generator to validate the decoded CRC information received from the semiconductor memory.
Claim 54
Dependent Claim
23 words
The method of claim 38, wherein the second CRC generator generates secondary CRC information with respect to data retrieved from the semiconductor memory.
Claim 55
Dependent Claim
18 words
The method of claim 41, further comprising forming the encoded information by also using the secondary CRC information.
Claim 56
Dependent Claim
118 words
An error correction encoding method comprising: generating v number of ECC bytes for each m-way interleaved Reed-Solomon codeword over a corresponding one of m number of interleaves, the roots of the Reed-Solomon codeword being α r-v+1 to α r , where v and m are integers and r and v are predetermined integers; generating k number of CRC bytes over a CRC input byte sequence, k being an integer, wherein the CRC input byte sequence is formed by taking a linear combination of the m number of interleaves, and wherein the k number of CRC bytes is generated by dividing the CRC input byte sequence by factors (x+α r+1 ) to (x+α r+k ) and taking the remainder.
Claim 57
Dependent Claim
118 words
An error correction encoding method comprising: generating v number of ECC bytes for each m-way interleaved Reed-Solomon codeword over a corresponding one of m number of interleaves, the roots of the Reed-Solomon codeword being α r-v+1 to α r , where v and m are integers and r and v are predetermined integers; generating k number of CRC bytes over a CRC input byte sequence, k being an integer, wherein the CRC input byte sequence is formed by taking a linear combination of the m number of interleaves, and wherein the k number of CRC bytes is generated by dividing the CRC input byte sequence by factors (x+α r+1 ) to (x+α r+k ) and taking the remainder.
Claim 58
Dependent Claim
12 words
The method of claim 43, wherein the integer k is programmably selected.
Claim 59
Dependent Claim
47 words
The method of claim 43, wherein the linear combination is obtained by summing over all products of the form M j ×D j where M j is a constant multiplier and D j is a byte from a jth interleave, wherein j ranges from 0 to m-1.
Claim 60
Dependent Claim
25 words
The method of claim 45, wherein M j is selected so that the linear combination of certain predetermined sets of m bytes is always non-zero.
Claim 61
Dependent Claim
25 words
The method of claim 46, wherein m is 3 and the sets consists of 3 bytes where no byte has more than a single "1".
Claim 62
Dependent Claim
37 words
The method of claim 46, wherein m is 3 and the sets consists of 3 bytes where one byte is all zeros and the remaining two bytes contain a non-zero sequence of length no more than 4.
Claim 63
Dependent Claim
137 words
An error correction encoding apparatus comprising: a CRC generator which generates k number of CRC bytes over a CRC input byte sequence, k being an integer, wherein the CRC input byte sequence is formed by dividing a data input stream into m number of interleaves and taking a linear combination of the m number of interleaves, and wherein the k number of CRC bytes is generated by dividing the CRC input byte sequence by factors (x+α r+1 ) to (x+α r+k ) and taking the remainder; an ECC generator which generates v number of ECC bytes for each m-way interleaved Reed-Solomon codeword over a corresponding one of m number of interleaves, the roots of the Reed-Solomon codeword being α r-v+1 to α r , where v and m are integers and r and v are predetermined integers.
Claim 64
Dependent Claim
137 words
An error correction encoding apparatus comprising: a CRC generator which generates k number of CRC bytes over a CRC input byte sequence, k being an integer, wherein the CRC input byte sequence is formed by dividing a data input stream into m number of interleaves and taking a linear combination of the m number of interleaves, and wherein the k number of CRC bytes is generated by dividing the CRC input byte sequence by factors (x+α r+1 ) to (x+α r+k ) and taking the remainder; an ECC generator which generates v number of ECC bytes for each m-way interleaved Reed-Solomon codeword over a corresponding one of m number of interleaves, the roots of the Reed-Solomon codeword being α r-v+1 to α r , where v and m are integers and r and v are predetermined integers.
Claim 65
Dependent Claim
12 words
The apparatus of claim 49, wherein the integer k is programmably selected.
Claim 66
Dependent Claim
47 words
The apparatus of claim 49, wherein the linear combination is obtained by summing over all products of the form M j ×D j where M j is a constant multiplier and D j is a byte from a jth interleave, wherein j ranges from 0 to m-1.
Claim 67
Dependent Claim
25 words
The apparatus of claim 51, wherein M j is selected so that the linear combination of certain predetermined sets of m bytes is always non-zero.
Claim 68
Dependent Claim
25 words
The apparatus of claim 52, wherein m is 3 and the sets consists of 3 bytes where no byte has more than a single "1".
Claim 69
Dependent Claim
37 words
The apparatus of claim 52, wherein m is 3 and the sets consists of 3 bytes where one byte is all zeros and the remaining two bytes contain a non-zero sequence of length no more than 4.
Claim 70
Dependent Claim
114 words
An error correction encoding method for encoding a data input stream, the method comprising: dividing the data input stream into m number of interleaves; generating k number of CRC bytes over the m number of interleaves; generating ECC bytes over the input data stream whereby it takes an error of a first predetermined number of bytes not to be detected by the ECC bytes; and wherein, the k number of CRC bytes and the ECC bytes are so formed over the interleaves whereby it takes an error of a second predetermined number of bytes not to be detected, the second predetermined number being equal to a sum of the first predetermined number and k.
Claim 71
Dependent Claim
114 words
An error correction encoding method for encoding a data input stream, the method comprising: dividing the data input stream into m number of interleaves; generating k number of CRC bytes over the m number of interleaves; generating ECC bytes over the input data stream whereby it takes an error of a first predetermined number of bytes not to be detected by the ECC bytes; and wherein, the k number of CRC bytes and the ECC bytes are so formed over the interleaves whereby it takes an error of a second predetermined number of bytes not to be detected, the second predetermined number being equal to a sum of the first predetermined number and k.
Claim 72
Dependent Claim
25 words
The method of claim 55, wherein the k number of CRC bytes are formed by taking a linear combination over the m number of interleaves.
Claim 73
Dependent Claim
21 words
The method of claim 56, wherein the linear combination is formed whereby no two single bit errors can cancel each other.
Claim 74
Dependent Claim
124 words
An error correction apparatus for encoding a data input stream, the apparatus comprising: an interleaver for dividing the data input stream into m number of interleaves; a CRC generator which generates k number of CRC bytes over the m number of interleaves; an ECC generator which generates ECC bytes over the input data stream whereby it takes an error of a first predetermined number of bytes not to be detected by the ECC bytes; and wherein, the k number of CRC bytes and the ECC bytes are so formed over the interleaves whereby it takes an error of a second predetermined number of bytes not to be detected, the second predetermined number being equal to a sum of the first predetermined number and k.
Claim 75
Dependent Claim
124 words
An error correction apparatus for encoding a data input stream, the apparatus comprising: an interleaver for dividing the data input stream into m number of interleaves; a CRC generator which generates k number of CRC bytes over the m number of interleaves; an ECC generator which generates ECC bytes over the input data stream whereby it takes an error of a first predetermined number of bytes not to be detected by the ECC bytes; and wherein, the k number of CRC bytes and the ECC bytes are so formed over the interleaves whereby it takes an error of a second predetermined number of bytes not to be detected, the second predetermined number being equal to a sum of the first predetermined number and k.
Claim 76
Dependent Claim
25 words
The apparatus of claim 58, wherein the k number of CRC bytes are formed by taking a linear combination over the m number of interleaves.
Claim 77
Dependent Claim
21 words
The apparatus of claim 59, wherein the linear combination is formed whereby no two single bit errors can cancel each other.
Claim 78
Dependent Claim
89 words
An error correction encoding method for encoding an input data stream for recordation on a storage medium, the method comprising: dividing an input data stream into interleaves; generating both CRC bytes and ECC bytes over same ones of the interleaves to increase a minimum distance of codewords written on the storage medium; the CRC bytes being generated whereby single bit random errors retrieved from a temporary memory do not cancel, the temporary memory being used in the method to store temporarily the input data stream and the CRC bytes.
Claim 79
Dependent Claim
89 words
An error correction encoding method for encoding an input data stream for recordation on a storage medium, the method comprising: dividing an input data stream into interleaves; generating both CRC bytes and ECC bytes over same ones of the interleaves to increase a minimum distance of codewords written on the storage medium; the CRC bytes being generated whereby single bit random errors retrieved from a temporary memory do not cancel, the temporary memory being used in the method to store temporarily the input data stream and the CRC bytes.
Claim 80
Dependent Claim
101 words
An error correction encoding apparatus for encoding an input data stream for recordation on a storage medium, the apparatus comprising: an interleaver for dividing an input data stream into interleaves; a CRC generator and an ECC generator for respectively generating both CRC bytes and ECC bytes over same ones of the interleaves to increase a minimum distance of codewords written on the storage medium, the CRC bytes being generated whereby single bit random errors retrieved from a temporary memory do not cancel, the temporary memory being used in the method to store temporarily the input data stream and the CRC bytes.
Claim 81
Dependent Claim
101 words
An error correction encoding apparatus for encoding an input data stream for recordation on a storage medium, the apparatus comprising: an interleaver for dividing an input data stream into interleaves; a CRC generator and an ECC generator for respectively generating both CRC bytes and ECC bytes over same ones of the interleaves to increase a minimum distance of codewords written on the storage medium, the CRC bytes being generated whereby single bit random errors retrieved from a temporary memory do not cancel, the temporary memory being used in the method to store temporarily the input data stream and the CRC bytes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |