US5723381A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud
Assignee: Siemens AG
•
Filing: 1995-09-27
•
Granted: 1998-03-03
•
Expires: 2015-09-27
Abstract
Abstract A method of forming a self-aligned overlapping bitline contact, includes steps of first depositing a sacrificial polysilicon on a spacer dielectric film, and thereafter patterning the polysilicon. The polysilicon film is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide on the polysilicon, and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon is etched and the spacer dielectric film is etched to form a self-aligned bitline contact.
Inventors
- 👤 Virinder Grewal
- 👤 Bernhard Poschenrieder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:34
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
61 words
A method of forming a semiconductor device, comprising steps of: depositing a spacer dielectric film over a gate material; depositing a sacrificial polysilicon film over said spacer dielectric film; patterning said polysilicon film; depositing an oxide on said polysilicon film; planarizing said oxide by chemical mechanical polishing (CMP); and removing said polysilicon film by isotropic etching to form said semiconductor device.
Claim 2
Independent Claim
61 words
A method of forming a semiconductor device, comprising steps of: depositing a spacer dielectric film over a gate material; depositing a sacrificial polysilicon film over said spacer dielectric film; patterning said polysilicon film; depositing an oxide on said polysilicon film; planarizing said oxide by chemical mechanical polishing (CMP); and removing said polysilicon film by isotropic etching to form said semiconductor device.
Claim 3
Dependent Claim
25 words
A method according to claim 1, wherein said step of etching include at least one of a wet etching step and a dry etching step.
Claim 4
Dependent Claim
15 words
A method according to claim 1, wherein said spacer dielectric film comprises SiO 2 .
Claim 5
Dependent Claim
23 words
A method according to claim 1, wherein said spacer dielectric film has a thickness between a range of 10 nm and 40 nm.
Claim 6
Dependent Claim
18 words
A method according to claim 4, wherein said spacer dielectric film has a thickness of approximately 20 nm.
Claim 7
Dependent Claim
29 words
A method according to claim 1, wherein said step of depositing said spacer dielectric film comprises a step of depositing said spacer dielectric film by chemical vapor deposition (CVD).
Claim 8
Dependent Claim
56 words
A method according to claim 1, wherein said gate material comprises a gate mask deposited over a gate polysilicon layer, said gate mask having a thickness in a range of approximately 100 nm to approximately 200 nm and said gate polysilicon layer having a thickness in a range of approximately 100 nm to approximately 200 nm.
Claim 9
Dependent Claim
27 words
A method according to claim 1, wherein said step of depositing said sacrificial polysilicon film comprises depositing, by low-pressure chemical vapor deposition (LPCVD), said sacrificial polysilicon film.
Claim 10
Dependent Claim
21 words
A method according to claim 1, wherein said step of planarizing said oxide comprises a step of isotropic etching said oxide.
Claim 11
Dependent Claim
25 words
A method according to claim 1, further comprising etching said spacer dielectric film to form a self-aligned bitline contact; and depositing said self-aligned bitline contact.
Claim 12
Independent Claim
60 words
A method of forming a self-aligned overlapping bitline contact, comprising steps of: depositing a sacrificial material on a film; patterning said material, said material being a sacrificial fill-in for a bitline contact stud; depositing an oxide on said material; planarizing said oxide by chemical-mechanical polishing (CMP); and isotropically etching said material and said film to form a self-aligned bitline contact.
Claim 13
Independent Claim
60 words
A method of forming a self-aligned overlapping bitline contact, comprising steps of: depositing a sacrificial material on a film; patterning said material, said material being a sacrificial fill-in for a bitline contact stud; depositing an oxide on said material; planarizing said oxide by chemical-mechanical polishing (CMP); and isotropically etching said material and said film to form a self-aligned bitline contact.
Claim 14
Dependent Claim
19 words
A method according to claim 11, wherein said material comprises polysilicon and said film comprises a spacer dielectric film.
Claim 15
Dependent Claim
26 words
A method according to claim 12, wherein said step of isotropically etching includes at least one of a wet etching step and a dry etching step.
Claim 16
Dependent Claim
22 words
A method according to claim 12, wherein said spacer dielectric film comprises one of SiO 2 and Si 3 N 4 .
Claim 17
Dependent Claim
23 words
A method according to claim 12, wherein said spacer dielectric film has a thickness between a range of 10 nm and 40 nm.
Claim 18
Dependent Claim
18 words
A method according to claim 15, wherein said spacer dielectric film has a thickness of approximately 20 nm.
Claim 19
Dependent Claim
57 words
A product formed by a process comprising steps of: depositing a sacrificial material on a film; patterning said material, said material being a sacrificial fill-in for a bitline contact stud; depositing an oxide on said material; planarizing said oxide by chemical-mechanical polishing (CMP); isotropically etching said material; and etching said film to form a self-aligned bitline contact.
Claim 20
Dependent Claim
57 words
A product formed by a process comprising steps of: depositing a sacrificial material on a film; patterning said material, said material being a sacrificial fill-in for a bitline contact stud; depositing an oxide on said material; planarizing said oxide by chemical-mechanical polishing (CMP); isotropically etching said material; and etching said film to form a self-aligned bitline contact.
References Cited (Backward Citations)
US5158898A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |