US5721953A
Expired / Lapsed
US
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Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready
Assignee: International Business Machines Corp
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Filing: 1996-04-03
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Granted: 1998-02-24
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Expires: 2016-04-03
Abstract
Abstract A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.
Inventors
- 👤 Richard Gregory Fogg, Jr.
- 👤 Mark David Sweet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:51
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
160 words
A host interface for a logic simulation machine having a plurality of simulation processors for transferring data between the logic simulation machine and a host computer, comprising: a parallel simulation bus means provided in the logic simulation machine coupled to each of the simulation processors in parallel for providing concurrent transfer of data by each of the simulation processors with the host computer, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; a First-In First-Out buffer means provided between the parallel simulation bus means and the host computer; and a control means coupled to the First-In First-Out buffer means for controlling the First-In First-Out buffer means wherein the First-In First-Out buffer means temporarily stores on demand data being concurrently transferred between a plurality of the simulation processors in the logic simulation machine and the host computer until a receiver of the data is ready to receive the data.
Claim 2
Dependent Claim
160 words
A host interface for a logic simulation machine having a plurality of simulation processors for transferring data between the logic simulation machine and a host computer, comprising: a parallel simulation bus means provided in the logic simulation machine coupled to each of the simulation processors in parallel for providing concurrent transfer of data by each of the simulation processors with the host computer, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; a First-In First-Out buffer means provided between the parallel simulation bus means and the host computer; and a control means coupled to the First-In First-Out buffer means for controlling the First-In First-Out buffer means wherein the First-In First-Out buffer means temporarily stores on demand data being concurrently transferred between a plurality of the simulation processors in the logic simulation machine and the host computer until a receiver of the data is ready to receive the data.
Claim 3
Dependent Claim
71 words
The host interface for a logic simulation machine according to claim 1 wherein the First-In First-Out buffer means further includes: a host to simulation First-In First-Out buffer for storing on demand data from the host computer and sending the data to the logic simulation machine; and a simulation to host First-In First-Out buffer for storing on demand data from the logic simulation machine and sending the data to the host computer.
Claim 4
Dependent Claim
47 words
The host interface for a logic simulation machine according to claim 1 wherein the host computer includes an I/O bus means for communicating with the logic simulation machine, and the First-In First-Out buffer means is provided between the parallel simulation bus means and the I/O bus means.
Claim 5
Independent Claim
153 words
A method of transferring data between a host computer and a logic simulation machine having a plurality of simulation processors including a parallel simulation bus means and a First-In First-Out buffer means connected between the parallel simulation bus means and the host computer, comprising the steps of: temporarily storing on demand data being concurrently sent from a plurality of the simulation processors in the logic simulation machine across the parallel simulation bus means to the host computer in the First-In First-Out buffer means until the host computer is ready to receive the data, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; and temporarily storing on demand data being sent from the host computer across the parallel simulation bus means to the logic simulation in the First-In First-Out buffer means until the logic simulation machine is ready to receive the data.
Claim 6
Independent Claim
153 words
A method of transferring data between a host computer and a logic simulation machine having a plurality of simulation processors including a parallel simulation bus means and a First-In First-Out buffer means connected between the parallel simulation bus means and the host computer, comprising the steps of: temporarily storing on demand data being concurrently sent from a plurality of the simulation processors in the logic simulation machine across the parallel simulation bus means to the host computer in the First-In First-Out buffer means until the host computer is ready to receive the data, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; and temporarily storing on demand data being sent from the host computer across the parallel simulation bus means to the logic simulation in the First-In First-Out buffer means until the logic simulation machine is ready to receive the data.
Claim 7
Dependent Claim
69 words
The method according to claim 4 further including the steps of: sending the data from the First-In First-Out buffer means to the host computer when the host computer is ready to receive the data from the logic simulation machine; and sending the data from the First-In First-Out buffer means to the logic simulation machine when the logic simulation machine is ready to receive the data from the host computer.
Claim 8
Dependent Claim
64 words
The method according to claim 4 wherein the First-In First-Out buffer means includes a simulation to host First-In First-Out buffer for temporarily storing on demand the data being sent from the logic simulation machine to the host computer and a host to simulation First-In First-Out buffer for temporarily storing on demand the data being sent from the host computer to the logic simulation machine.
Claim 9
Dependent Claim
170 words
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer, comprising: a plurality of simulation processors provided in the logic simulation machine for parallel processing; a parallel simulation bus means provided in the logic simulation machine coupled to each of the simulation processors in parallel for providing concurrent transfer of data by each of the simulation processors with the host computer, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; a First-In First-Out buffer means provided between the parallel simulation bus means and the host computer; and a control means coupled to the First-In First-Out buffer means for controlling the First-In First-Out buffer means wherein the First-In First-Out buffer means temporarily stores on demand data being concurrently transferred in parallel between a plurality of the simulation processors in the logic simulation machine and the host computer until a receiver of the data is ready to receive the data.
Claim 10
Dependent Claim
170 words
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer, comprising: a plurality of simulation processors provided in the logic simulation machine for parallel processing; a parallel simulation bus means provided in the logic simulation machine coupled to each of the simulation processors in parallel for providing concurrent transfer of data by each of the simulation processors with the host computer, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; a First-In First-Out buffer means provided between the parallel simulation bus means and the host computer; and a control means coupled to the First-In First-Out buffer means for controlling the First-In First-Out buffer means wherein the First-In First-Out buffer means temporarily stores on demand data being concurrently transferred in parallel between a plurality of the simulation processors in the logic simulation machine and the host computer until a receiver of the data is ready to receive the data.
Claim 11
Dependent Claim
77 words
The host interface for a logic simulation machine according to claim 7 wherein the First-In First-Out buffer means further includes: a host to simulation First-In First-Out buffer for temporarily storing on demand data from the host computer and sending the temporarily stored data to the logic simulation machine; and a simulation to host First-In First-Out buffer for temporarily storing on demand data from the logic simulation machine and sending the temporarily stored data to the host computer.
Claim 12
Dependent Claim
47 words
The host interface for a logic simulation machine according to claim 7 wherein the host computer includes an I/O bus means for communicating with the logic simulation machine, and the First-In First-Out buffer means is provided between the parallel simulation bus means and the I/O bus means.
Claim 13
Dependent Claim
181 words
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer, comprising: a plurality of simulation processors provided in the logic simulation machine for parallel processing; a parallel simulation bus means provided in the logic simulation machine coupled to each of the simulation processors in parallel for providing concurrent transfer of data by each of the simulation processors with the host computer, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; a plurality of First-In First-Out buffer means provided between each of the parallel simulation bus means and the host computer; and a plurality of control means, each control means coupled to one of the First-In First-Out buffer means for controlling the coupled First-In First-Out buffer means wherein the coupled First-In First-Out buffer means temporarily stores data being concurrently transferred in parallel between a plurality of the simulation processors in the logic simulation machine and the host computer until a receiver of the data is ready to receive the data.
Claim 14
Dependent Claim
181 words
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer, comprising: a plurality of simulation processors provided in the logic simulation machine for parallel processing; a parallel simulation bus means provided in the logic simulation machine coupled to each of the simulation processors in parallel for providing concurrent transfer of data by each of the simulation processors with the host computer, each simulation processor generating simulation data and concurrently transferring said simulation data on a different portion of the parallel simulation bus; a plurality of First-In First-Out buffer means provided between each of the parallel simulation bus means and the host computer; and a plurality of control means, each control means coupled to one of the First-In First-Out buffer means for controlling the coupled First-In First-Out buffer means wherein the coupled First-In First-Out buffer means temporarily stores data being concurrently transferred in parallel between a plurality of the simulation processors in the logic simulation machine and the host computer until a receiver of the data is ready to receive the data.
Claim 15
Dependent Claim
73 words
The host interface for a logic simulation machine according to claim 10 wherein the First-In First-Out buffer means further includes: a host to simulation First-In First-Out buffer for temporarily storing data from the host computer and sending the temporarily stored data to the logic simulation machine; and a simulation to host First-In First-Out buffer for temporarily storing data from the logic simulation machine and sending the temporarily stored data to the host computer.
Claim 16
Dependent Claim
47 words
The host interface for a logic simulation machine according to claim 10 wherein the host computer includes an I/O bus means for communicating with the logic simulation machine, and the First-In First-Out buffer means is provided between the parallel simulation bus means and the I/O bus means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |