US5721855A
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US
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Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
Assignee: Intel Corp
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Filing: 1996-07-12
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Granted: 1998-02-24
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Expires: 2016-07-12
Abstract
Abstract A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.
Inventors
- 👤 Glenn J. Hinton
- 👤 David B. Papworth
- 👤 Andrew F. Glew
- 👤 Michael A. Fetterman
- 👤 Robert P. Colwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F9/30003; G06F9/3005; G06F9/30054; G06F9/30058; G06F9/30145; G06F9/30149; G06F9/30152; G06F9/32; G06F9/322; G06F9/323; G06F9/3802; G06F9/3804; G06F9/3806; G06F9/3812; G06F9/3816; G06F9/3818; G06F9/3822; G06F9/3824; G06F9/383; G06F9/3834; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3848; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3877; G06F9/3885; G06F9/3889; G06F9/3891; G09; G09F; G09F13/00; G09F13/04; G09F13/0418; G09F13/0472
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
248 words
A pipelined method for executing a plurality of instructions in a computer system, said method comprising the steps of: decoding the plurality of instructions in order in an in-order processing portion of a processor to produce a plurality of operations, issuing the plurality of operations to an out-of-order execution core in the processor at the same time, wherein the step of issuing comprises writing the plurality of operations into a reservation station and simultaneously reading source data from a reorder buffer, separate from the reservation station, for use in execution of the plurality of operations only if indicated as ready in a register file maintained outside the reorder buffer in the first in-order portion of the processor; executing the plurality of operations with at least one of said plurality of operations being executed out-of-order, wherein the step of executing includes the steps of scheduling and dispatching individual operations as data required for execution is ready, executing each of said individual operations, and writing back results from execution, wherein the step of writing back includes the steps of associatively writing data results directly into the reservation station for use by one or more individual operations in the reservation station during execution and writing data results into the reorder buffer; and further wherein the steps of scheduling and dispatching, executing and writing back are performed in consecutive pipestages; and committing results from execution of the plurality of operations to architectural state in order of issuance to the out-of-order execution core.
Claim 2
Dependent Claim
248 words
A pipelined method for executing a plurality of instructions in a computer system, said method comprising the steps of: decoding the plurality of instructions in order in an in-order processing portion of a processor to produce a plurality of operations, issuing the plurality of operations to an out-of-order execution core in the processor at the same time, wherein the step of issuing comprises writing the plurality of operations into a reservation station and simultaneously reading source data from a reorder buffer, separate from the reservation station, for use in execution of the plurality of operations only if indicated as ready in a register file maintained outside the reorder buffer in the first in-order portion of the processor; executing the plurality of operations with at least one of said plurality of operations being executed out-of-order, wherein the step of executing includes the steps of scheduling and dispatching individual operations as data required for execution is ready, executing each of said individual operations, and writing back results from execution, wherein the step of writing back includes the steps of associatively writing data results directly into the reservation station for use by one or more individual operations in the reservation station during execution and writing data results into the reorder buffer; and further wherein the steps of scheduling and dispatching, executing and writing back are performed in consecutive pipestages; and committing results from execution of the plurality of operations to architectural state in order of issuance to the out-of-order execution core.
Claim 3
Dependent Claim
112 words
The method defined in claim 1 wherein the step of decoding further includes the steps of: performing an instruction cache memory lookup to fetch the plurality of instructions, performing instruction length decoding, rotating the plurality of instructions, and decoding the plurality of instructions in an instruction decoder to generate the plurality of operations, performing register renaming, allocating resources and sending a portion of each of the plurality of operations to the reservation station, wherein the steps of performing an instruction cache memory lookup, performing instruction length decoding, rotating the plurality of instructions, decoding the plurality of instructions, and performing register renaming are performed in consecutive pipestages to generate the plurality of instructions.
Claim 4
Dependent Claim
28 words
The method defined in claim 2 wherein the step of performing instruction length decoding includes marking the plurality of instructions to identify each of the plurality of instructions.
Claim 5
Dependent Claim
29 words
The method defined in claim 2 wherein the step of rotating is performed based on an instruction fetch pointer and a number of instructions consumed by the instruction decoder.
Claim 6
Dependent Claim
20 words
The method defined in claim 2 wherein the step of decoding the plurality of instructions is performed in two pipestages.
Claim 7
Dependent Claim
33 words
The method defined in claim 2 wherein the step of performing register renaming, allocating resources and sending each of the plurality of operations to the reservation station is performed in a single pipestage.
Claim 8
Dependent Claim
16 words
The method defined in claim 1 wherein the step of retiring is performed in two pipestages.
Claim 9
Dependent Claim
233 words
A pipelined method for executing a plurality of instructions in a computer system, said method comprising the steps of: decoding the plurality of instructions in order to produce a plurality of operations, wherein the step of decoding includes the steps of maintaining a readiness indication of source data for the plurality of operations in a storage area outside a reorder buffer in an in-order processing portion of a processor; writing the plurality of operations into a reservation station in an out-of-order execution core of the processor at the same time and reading data from the reorder buffer for use in execution of the plurality of operations, simultaneously to writing the plurality of operations into the reservation station, only if data is indicated as ready in the storage area; executing the plurality of operations with at least one of the plurality of operations being executed out-of-order, wherein the step of executing includes the steps of scheduling and dispatching individual operations as data required for execution of each of the individual operations is ready, executing each of said individual operations, and writing back results from execution including associatively writing at least one result to the reservation station, wherein the steps of scheduling and dispatching, executing and writing back are performed in consecutive pipestages; and committing results from execution of the plurality of operations to architectural state in order of issuance of the plurality of operations.
Claim 10
Dependent Claim
233 words
A pipelined method for executing a plurality of instructions in a computer system, said method comprising the steps of: decoding the plurality of instructions in order to produce a plurality of operations, wherein the step of decoding includes the steps of maintaining a readiness indication of source data for the plurality of operations in a storage area outside a reorder buffer in an in-order processing portion of a processor; writing the plurality of operations into a reservation station in an out-of-order execution core of the processor at the same time and reading data from the reorder buffer for use in execution of the plurality of operations, simultaneously to writing the plurality of operations into the reservation station, only if data is indicated as ready in the storage area; executing the plurality of operations with at least one of the plurality of operations being executed out-of-order, wherein the step of executing includes the steps of scheduling and dispatching individual operations as data required for execution of each of the individual operations is ready, executing each of said individual operations, and writing back results from execution including associatively writing at least one result to the reservation station, wherein the steps of scheduling and dispatching, executing and writing back are performed in consecutive pipestages; and committing results from execution of the plurality of operations to architectural state in order of issuance of the plurality of operations.
Claim 11
Dependent Claim
112 words
The method defined in claim 8 wherein the step of decoding further includes the steps of: performing an instruction cache memory lookup to fetch the plurality of instructions, performing instruction length decoding, rotating the plurality of instructions, and decoding the plurality of instructions in an instruction decoder to generate the plurality of operations, performing register renaming, allocating resources and sending a portion of each of the plurality of operations to the reservation station, wherein the steps of performing an instruction cache memory lookup, performing instruction length decoding, rotating the plurality of instructions, decoding the plurality of instructions, and performing register renaming are performed in consecutive pipestages to generate the plurality of instructions.
Claim 12
Dependent Claim
28 words
The method defined in claim 9 wherein the step of performing instruction length decoding includes marking the plurality of instructions to identify each of the plurality of instructions.
Claim 13
Dependent Claim
29 words
The method defined in claim 9 wherein the step of rotating is performed based on an instruction fetch pointer and a number of instructions consumed by the instruction decoder.
Claim 14
Dependent Claim
20 words
The method defined in claim 9 wherein the step of decoding the plurality of instructions is performed in two pipestages.
Claim 15
Dependent Claim
33 words
The method defined in claim 9 wherein the step of performing register renaming, allocating resources and sending each of the plurality of operations to the reservation station is performed in a single pipestage.
Claim 16
Dependent Claim
16 words
The method defined in claim 8 wherein the step of retiring is performed in two pipestages.
Claim 17
Independent Claim
302 words
A method for executing a plurality of instructions in a computer system, said method comprising the steps of: providing the plurality of instructions as a plurality of operations in an in-order pipeline, wherein the step of providing the plurality of instructions includes the steps of performing an instruction cache memory lookup to fetch the plurality of instructions, performing instruction length decoding, rotating the plurality of instructions, and decoding the plurality of instructions in an instruction decoder to generate the plurality of operations, performing register renaming, allocating resources and maintaining a readiness indication of source data for the plurality of operations in a storage area outside a reorder buffer, issuing the plurality of operations including the steps sending a portion of each of the plurality of operations to a reservation station at the same time and reading source data from the reorder buffer if valid as indicated in the storage area, wherein the steps of performing an instruction cache memory lookup, performing instruction length decoding, rotating the plurality of instructions, decoding the plurality of instructions, and performing register renaming are performed in consecutive pipestages; executing the plurality of operations in an out-of-order pipeline to produce execution results, wherein the step of executing includes the steps of determining execution readiness of each of the plurality of operations and scheduling individual operations in the plurality of operations that have source data available, dispatching individual operations to an execution unit as data required for each said individual operation is ready, executing said individual operations and writing back the results, including associatively writing at least one result to the reservation station, wherein the steps of determining execution readiness, dispatching and executing are performed in consecutive pipestages; and retiring each of the plurality of operations, wherein results from execution are committed to architectural state and order is reestablished.
Claim 18
Independent Claim
302 words
A method for executing a plurality of instructions in a computer system, said method comprising the steps of: providing the plurality of instructions as a plurality of operations in an in-order pipeline, wherein the step of providing the plurality of instructions includes the steps of performing an instruction cache memory lookup to fetch the plurality of instructions, performing instruction length decoding, rotating the plurality of instructions, and decoding the plurality of instructions in an instruction decoder to generate the plurality of operations, performing register renaming, allocating resources and maintaining a readiness indication of source data for the plurality of operations in a storage area outside a reorder buffer, issuing the plurality of operations including the steps sending a portion of each of the plurality of operations to a reservation station at the same time and reading source data from the reorder buffer if valid as indicated in the storage area, wherein the steps of performing an instruction cache memory lookup, performing instruction length decoding, rotating the plurality of instructions, decoding the plurality of instructions, and performing register renaming are performed in consecutive pipestages; executing the plurality of operations in an out-of-order pipeline to produce execution results, wherein the step of executing includes the steps of determining execution readiness of each of the plurality of operations and scheduling individual operations in the plurality of operations that have source data available, dispatching individual operations to an execution unit as data required for each said individual operation is ready, executing said individual operations and writing back the results, including associatively writing at least one result to the reservation station, wherein the steps of determining execution readiness, dispatching and executing are performed in consecutive pipestages; and retiring each of the plurality of operations, wherein results from execution are committed to architectural state and order is reestablished.
Claim 19
Dependent Claim
28 words
The method defined in claim 15 wherein the step of performing instruction length decoding includes marking the plurality of instructions to identify each of the plurality of instructions.
Claim 20
Dependent Claim
29 words
The method defined in claim 15 wherein the step of rotating is performed based on an instruction fetch pointer and a number of instructions consumed by the instruction decoder.
Claim 21
Dependent Claim
20 words
The method defined in claim 15 wherein the step of decoding the plurality of instructions is performed in two pipestages.
Claim 22
Dependent Claim
33 words
The method defined in claim 15 wherein the step of performing register renaming, allocating resources and sending each of the plurality of operations to the reservation station is performed in a single pipestage.
Claim 23
Dependent Claim
28 words
The method defined in claim 15 wherein the step of executing operations determined to be data ready and writing back the results is performed in a single pipestage.
Claim 24
Dependent Claim
16 words
The method defined in claim 15 wherein the step of retiring is performed in two pipestages.
Claim 25
Dependent Claim
40 words
The method defined in claim 15 wherein the steps of performing an instruction cache memory lookup, performing instruction length decoding, rotating the plurality of instructions, decoding the plurality of instructions, and performing register renaming are performed in seven consecutive pipestages.
Claim 26
Dependent Claim
130 words
A pipeline method for executing a plurality of instructions in a computer system, said method comprising the steps of: decoding the plurality of instructions in order into a plurality of micro-operations; writing the plurality of operations into a reservation station at the same time; reading source data, simultaneously to the step of writing the plurality of micro-operations into a reservation station, from a reorder buffer only if indicated as ready in a register file outside the reorder buffer; executing the plurality of micro-operations with at least one of the plurality of micro-operations being executed out-of-order; writing back results from execution of the plurality of operations including associatively writing at least one result to the reservation station; committing results from execution of the plurality of operations to the out-of-order execution core.
Claim 27
Dependent Claim
130 words
A pipeline method for executing a plurality of instructions in a computer system, said method comprising the steps of: decoding the plurality of instructions in order into a plurality of micro-operations; writing the plurality of operations into a reservation station at the same time; reading source data, simultaneously to the step of writing the plurality of micro-operations into a reservation station, from a reorder buffer only if indicated as ready in a register file outside the reorder buffer; executing the plurality of micro-operations with at least one of the plurality of micro-operations being executed out-of-order; writing back results from execution of the plurality of operations including associatively writing at least one result to the reservation station; committing results from execution of the plurality of operations to the out-of-order execution core.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |