Adapter having data aligner including register being loaded to or from memory with an offset in accordance with predetermined network fragmentation parameters

Claim 2

An adapter for connecting a network system to a peripheral component, said adaptor including a memory for storing data received from or to be transmitted to said network and a data aligner connected between said memory and said network, wherein said aligner includes a register for storing data, said register being loaded to or from said memory with an offset in accordance with predetermined network fragmentation parameters, wherein said register is configured as contiguous serial register portions.

Claim 3

An adapter as claimed in claim 1, wherein said register further comprises an interface register for loading and receiving data to and from one of register portions.

Claim 4

An adapter as claimed in claim 2, wherein said register portions are of a reduced width compared to memory access width.

Claim 5

An adapter as claimed in claim 3, wherein the widths of the register portions are half the memory access width.

Claim 6

An adapter as claimed in claim 4, wherein data is loaded from the network at a register portion at one end of the contiguous portions and data is output to the network from a register portion at an opposite end thereof.

Claim 7

An adapter for connecting a network system to a peripheral component, said adapter including a memory for storing data received from or to be transmitted to said network and a data aligner connected between said memory and said network, wherein said aligner includes a register for storing data, said register being loaded to or from said memory with an offset in accordance with predetermined network fragmentation parameters, wherein offset is precalculated in a transfer controller, and wherein said controller also calculates delay.

Claim 8

An adapter for connecting a network system to a peripheral component, said adapter including a memory for storing data received from or to be transmitted to said network and a data aligner connected between said memory and said network, wherein said aligner includes a register for storing data, said register being loaded to or from said memory with an offset in accordance with predetermined network fragmentation parameters, wherein offset is precalculated in a transfer controller, and wherein said controller also calculates delay.

Claim 9

A data aligner for transferring data from a first data path having a predetermined width to a second data path having a width larger than said predetermined width, while aligning the data at any selected byte boundary at the second path, comprising: a register arrangement, comprising a plurality of registers, arranged serially such that data can be shifted in the direction of one end thereof in response to a shift command; said register arrangement being capable of receiving, in response to a load signal, data from said first path into one end of said register arrangement with a selectable offset of said data by a selectable mumber of bytes in the direction said shifting is done; and said register arrangement being capable of reading, in response to a read signal, said data from said register arrangement to said second path.

Claim 10

A data aligner for transferring data from a first data path having a predetermined width to a second data path having a width larger than said predetermined width, while aligning the data at any selected byte boundary at the second path, comprising: a register arrangement, comprising a plurality of registers, arranged serially such that data can be shifted in the direction of one end thereof in response to a shift command; said register arrangement being capable of receiving, in response to a load signal, data from said first path into one end of said register arrangement with a selectable offset of said data by a selectable mumber of bytes in the direction said shifting is done; and said register arrangement being capable of reading, in response to a read signal, said data from said register arrangement to said second path.

Claim 11

A data aligner according to claim 7, wherein said register arrangement can have one or more bytes selectably masked during a load of data to said register arrangement.

Claim 12

A data aligner according to claim 7, further comprising means for determining the delay of data in the data aligner, and providing a signal indicative of said delay.

Claim 13

A data aligner for transferring data from a first data path having a width of M bits to a second data path having a width of N bits, where N is larger than M, while aligning the data at any selected byte boundary at the second path, comprising: a register arrangement comprising a first M bit register, a second M bit register, and a third M bit register, arranged such that data can be shifted from said third register to said second register, and from said second register to said first register in response to a shift command; means for loading data from said first path into said third register and for selectably offsetting said data by a selectable number of bytes in the direction of said first register; means for shifting said data in the direction of said first register by M bits; and means for reading said data from said register arrangement to said second path.

Claim 14

A data aligner for transferring data from a first data path having a width of M bits to a second data path having a width of N bits, where N is larger than M, while aligning the data at any selected byte boundary at the second path, comprising: a register arrangement comprising a first M bit register, a second M bit register, and a third M bit register, arranged such that data can be shifted from said third register to said second register, and from said second register to said first register in response to a shift command; means for loading data from said first path into said third register and for selectably offsetting said data by a selectable number of bytes in the direction of said first register; means for shifting said data in the direction of said first register by M bits; and means for reading said data from said register arrangement to said second path.

Claim 15

A data aligner according to claim 10, further comprising means for selectably masking one or more bytes during a load of data to said register arrangement.

Claim 16

A data aligner according to claim 10, further comprising means for determining the delay of data in the data aligner, and providing a signal indicative of said delay.

Claim 17

A data aligner for transferring data from a first data path having a width of 32 bits to a second data path having a width of 64 bits, while aligning the data at any selected byte boundary at the second path, comprising: a register arrangement comprising a first thirty-two bit register, a second thirty-two bit register, and a third thirty-two bit register, arranged such that data can be shifted from said third register to said second register, and from said second register to said first register; means for loading data from said first path into said third register and for selectably offsetting said data by zero, one, two or three bytes in the direction of said first register; means for shifting said data in the direction of said first register by thirty-two bits; and means for reading said data from said register arrangement to said second path.

Claim 18

A data aligner for transferring data from a first data path having a width of 32 bits to a second data path having a width of 64 bits, while aligning the data at any selected byte boundary at the second path, comprising: a register arrangement comprising a first thirty-two bit register, a second thirty-two bit register, and a third thirty-two bit register, arranged such that data can be shifted from said third register to said second register, and from said second register to said first register; means for loading data from said first path into said third register and for selectably offsetting said data by zero, one, two or three bytes in the direction of said first register; means for shifting said data in the direction of said first register by thirty-two bits; and means for reading said data from said register arrangement to said second path.

Claim 19

A data aligner according to claim 13, further comprising means for selectably masking one or more bytes during a load of data to said register arrangement.

Claim 20

A data aligner according to claim 13, further comprising means for determining the delay of data in the data aligner, and providing a signal indicative of said delay.

Claim 21

A data aligner for transferring data between a first data path having a predetermined width and a second data path having a width larger than said predetermined width, while appropriately aligning the data at any byte boundary at the second path, comprising: a register arrangement, comprising a plurality of registers, arranged serially such that data can be shifted in the direction of one end thereof in response to a shift command; said register arrangement being capable of receiving, in response to a first signal, data from said first path into one end of said register arrangement with a selectable offset of said data by a selectable number of bytes in the direction said shifting is done, or of receiving, in response to a second signal, data from said second path into said register arrangement with a selectable offset of said data by a selectable number of bytes within said register arrangement; and said register arrangement being capable of reading, in response to a read signal, said data from said register arrangement to said first path or to said second path.

Claim 22

A data aligner for transferring data between a first data path having a predetermined width and a second data path having a width larger than said predetermined width, while appropriately aligning the data at any byte boundary at the second path, comprising: a register arrangement, comprising a plurality of registers, arranged serially such that data can be shifted in the direction of one end thereof in response to a shift command; said register arrangement being capable of receiving, in response to a first signal, data from said first path into one end of said register arrangement with a selectable offset of said data by a selectable number of bytes in the direction said shifting is done, or of receiving, in response to a second signal, data from said second path into said register arrangement with a selectable offset of said data by a selectable number of bytes within said register arrangement; and said register arrangement being capable of reading, in response to a read signal, said data from said register arrangement to said first path or to said second path.

Claim 23

An adapter for connecting a network system to a peripheral component, said adapter including a memory for storing data received from or to be transmitted to said network and a data aligner connected between said memory and said network, wherein said aligner includes a register arrangement for storing data, said register arrangement being loaded to or from said memory with an offset in accordance with predetermined network fragmentation parameters, said register arrangement comprising: a plurality of registers, arranged serially such that data can be shifted in the direction of one end thereof in response to a shift command; said register arrangement being capable of receiving, in response to a first signal, data from a first path into one end of said register arrangement with a selectable offset of said data by a selectable number of bytes in the direction said shifting is done, or of receiving, in response to a second signal, data from a second path into said register arrangement with a selectable offset of said data by a selectable number of bytes within said register arrangement; and said register arrangement being capable of reading, in response to a read signal, said data from said register arrangement to said first path or to said second path.

Claim 24

An adapter for connecting a network system to a peripheral component, said adapter including a memory for storing data received from or to be transmitted to said network and a data aligner connected between said memory and said network, wherein said aligner includes a register arrangement for storing data, said register arrangement being loaded to or from said memory with an offset in accordance with predetermined network fragmentation parameters, said register arrangement comprising: a plurality of registers, arranged serially such that data can be shifted in the direction of one end thereof in response to a shift command; said register arrangement being capable of receiving, in response to a first signal, data from a first path into one end of said register arrangement with a selectable offset of said data by a selectable number of bytes in the direction said shifting is done, or of receiving, in response to a second signal, data from a second path into said register arrangement with a selectable offset of said data by a selectable number of bytes within said register arrangement; and said register arrangement being capable of reading, in response to a read signal, said data from said register arrangement to said first path or to said second path.

Claim 25

An adapter according to claim 17, further comprising means for selectably masking one or more bytes during a load of data to said register arrangement.

Claim 26

An adapter according to claim 17, further comprising means for determining the delay of data in the data aligner, and providing a signal indicative of said delay.