Serial transfer system

Claim 2

A serial transfer system for performing serial data transfer between transmission and reception stages which phase locked loops for generating reference clock signals, said system comprising: transmission means for converting parallel data from said transmission stage into a serial data signal, for appending a data marker to the serial data signal in response to the reference clock signal from said phase locked loop of said transmission stage, and for transmitting the converted serial data signal through a coaxial cable; and reception means for receiving the serial data signal from said transmission means through the coaxial cable, converting the received serial signal into the original parallel data using the appended data marker and the reference clock signal from said phase locked loop of said reception stage and outputting the converted parallel data to said reception stage, wherein said transmission means includes: timing generation means for generating a clock signal for serial transfer in response to the reference clock signal from said phase locked loop of said transmission stage; parallel/serial conversion means for converting the parallel data from said transmission stage into the serial data signal and appending the data marker to the parallel data in response to the clock signal from said timing generation means; filtering means for removing a direct current component from the serial data signal from said parallel/serial conversion means; marker shaping means for varying the number of voltage levels of an output signal from said filtering means to facilitate data marker slicing; and driving means for buffering and driving an output signal from said marker shaping means to transmit the output signal from said marker shaping means through the coaxial cable.

Claim 3

A serial transfer system as set forth in claim 1, wherein said timing generation means includes: an amplifier for amplifying the reference clock signal from said phase locked loop of said transmission stage by a transistor transistor logic level; and a clock generator for generating the clock signal for the serial transfer in response to an output signal from said amplifier and outputting the generated clock signal to said parallel/serial conversion means.

Claim 4

A serial transfer system as set forth in claim 2, wherein the clock signal from said clock generator has a frequency of 37.5 MHz.

Claim 5

A serial transfer system as set forth in claim 1, wherein said marker shaping means varies the number of the voltage levels of the output signal from said filtering means from 3 to 5 to facilitate the data marker slicing.

Claim 6

A serial transfer system as set forth in claim 4, wherein said marker shaping means includes: a first analog switch for performing a switching operation in response to the output signal from said filtering means to output a 2-level signal of +10V; a second analog switch for performing a switching operation in response to the output signal from said filtering means to output a 1-level signal of +5V; a third analog switch for performing a switching operation in response to the output signal from said filtering means to output a 0-level signal of 0V; a fourth analog switch for performing a switching operation in response to the output signal from said filtering means to output a -1-level signal of -5V; and a fifth analog switch for performing a switching operation in response to the output signal from said filtering means to output a -2-level signal of -10V.

Claim 7

A serial transfer system as set forth in claim 1, wherein said filtering means includes: an adder for performing a modulo-2 operation with respect to the serial data signal from said parallel/serial conversion means; a first delay for delaying an output signal from said adder and feeding back the delayed signal to said adder; a second delay for delaying the output signal from said adder; and a subtracter for subtracting the output signal from said adder from an output signal from said second delay.

Claim 8

A serial transfer system as set forth in claim 1, wherein the transmission means converts parallel data into a serial data signal and appends a data marker at the same time.

Claim 9

A serial transfer system for performing serial data transfer between transmission and reception stages which have phase locked loops for generating reference clock signals said system comprising: transmission means for converting parallel data from said transmission stage into a serial data signal, for appending a data marker to the serial data signal in response to the reference stage, and for transmitting the converted serial data signal through a coaxial cable; and reception means for receiving the serial data signal from said transmission means through the coaxial cable, converting the received serial data signal into the original parallel data using the appended data marker and the reference clock signal from said phase locked loop of said reception stage and outputting the converted parallel data to said reception stage; said reception means including: amplification means for receiving the serial data signal from said transmission means through the coaxial cable and amplifying the received serial data signal; serial/parallel conversion means for slicing an output signal from said amplification means, for converting the sliced signal into the original parallel data, and for outputting the converted parallel data to said reception stage; timing generation means for controlling said phase locked loop of said reception stage according to the data marker from said serial/parallel conversion means, for generating a clock signal for parallel transfer in accordance with the controlled result, and for outputting the generated clock signal to said serial/parallel conversion means, wherein said serial/parallel conversion means includes: a data slicer for slicing a data portion of the output signal from said amplification means; a marker slicer for slicing a data portion of the output signal from said amplification means; a marker slicer for slicing a data marker portion of the output signal from said amplification means; and a data detector for detecting serial data from an output signal from said data slicer in response to the clock from said timing generation means, converting the detecting serial data into the original parallel data and output the converted parallel data to said reception stage.

Claim 10

A serial transfer system for performing serial data transfer between transmission and reception stages which have phase locked loops for generating reference clock signals said system comprising: transmission means for converting parallel data from said transmission stage into a serial data signal, for appending a data marker to the serial data signal in response to the reference stage, and for transmitting the converted serial data signal through a coaxial cable; and reception means for receiving the serial data signal from said transmission means through the coaxial cable, converting the received serial data signal into the original parallel data using the appended data marker and the reference clock signal from said phase locked loop of said reception stage and outputting the converted parallel data to said reception stage; said reception means including: amplification means for receiving the serial data signal from said transmission means through the coaxial cable and amplifying the received serial data signal; serial/parallel conversion means for slicing an output signal from said amplification means, for converting the sliced signal into the original parallel data, and for outputting the converted parallel data to said reception stage; timing generation means for controlling said phase locked loop of said reception stage according to the data marker from said serial/parallel conversion means, for generating a clock signal for parallel transfer in accordance with the controlled result, and for outputting the generated clock signal to said serial/parallel conversion means, wherein said serial/parallel conversion means includes: a data slicer for slicing a data portion of the output signal from said amplification means; a marker slicer for slicing a data portion of the output signal from said amplification means; a marker slicer for slicing a data marker portion of the output signal from said amplification means; and a data detector for detecting serial data from an output signal from said data slicer in response to the clock from said timing generation means, converting the detecting serial data into the original parallel data and output the converted parallel data to said reception stage.

Claim 11

A serial transfer system as set forth in claim 8, wherein said timing generation means includes: a vertical synchronous signal detector for detecting a vertical synchronous signal from the output signal from said data slicer in said serial/parallel conversion means in response to an output signal from said marker slicer in said serial/parallel conversion means and for outputting the detected vertical synchronous signal as a reference control signal for controlling generation of the reference clock signal in said phase locked loop of said reception stage; and an amplifier for amplifying the reference clock from said phase locked loop of said reception stage to a transistor transistor logic level to generate the clock signal for the parallel transfer and outputting the generated clock signal to said data detector in said serial/parallel conversion means.

Claim 12

A serial transfer system as set forth in claim 9, wherein the clock signal from said amplifier has a frequency of 2.69 MHz.

Claim 13

A serial transfer system as set forth in claim 8, wherein said data slicer includes: a first comparator for comparing a level of the output signal from said amplification means with a reference voltage of 2.5V; a second comparator for comparing the level of the output signal from said amplification means with a reference voltage of -2.5V; and an OR gate for ORing output signals from said first and second comparators and outputting the ORed signal to said data detector and said timing generation means.

Claim 14

A serial transfer system as set forth in claim 11, wherein said first and second comparators have upper and lower limit voltages of +5V and -5V for the comparison, respectively.

Claim 15

A serial transfer system as set forth in claim 8, wherein said marker slicer includes: a first comparator for comparing a level of the output signal from said amplification means with a reference voltage of 7.5V; a second comparator for comparing the level of the output signal from said amplification means with a reference voltage of -7.5V; and an OR gate for ORing output signals from said first and second comparators and outputting the ORed signal to said timing generation means.

Claim 16

A serial transfer system as set forth in claim 13, wherein said first and second comparators have upper and lower limit voltages of +10V and -10V for the comparison, respectively.