US5719633A
Expired / Lapsed
US
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Video signal format conversion apparatus using simplified shifting and processing control
Assignee: Panasonic Holdings Corp
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Filing: 1995-12-20
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Granted: 1998-02-17
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Expires: 2015-12-20
Abstract
Abstract A video signal format conversion apparatus, includes a memory for writing an input data by a first clock equal to a sampling rate of the input data and reading the input data by a second clock which is different from the first clock; a shift register for shifting the data read by the memory by the second clock; a multiplication and summation circuit for multiplying each of a plurality of data output from the shift register by a factor corresponding thereto among the plurality of factors and outputting a sum of values obtained by the multiplication by the second clock.
Inventors
- 👤 Toshirou Nishio
- 👤 Masashi Kubota
- 👤 Hidekazu Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:58
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/0122; G; G06; G06T; G06T3/00; G06T3/40; H04N5/00; H04N5/14; H04N7/0102; H04N7/0105
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
137 words
A video signal format conversion apparatus, comprising: a memory for writing an input data by a first clock equal to a sampling rate of the input data and reading the input data by a second clock which is different from the first clock; a shift register which is coupled to the memory, and is driven by the second clock, wherein a shift operation is performed in each cycle of the second clock, and no signals other than the second clock are needed for the shift operation; a multiplication and summation circuit which is coupled to the shift register for cyclically multiplying each of a plurality of data output from the shift register by a factor utilizing pipeline processing synchronous with the second clock, thereby calculating a sum of values obtained by the multiplication by the second clock.
Claim 2
Dependent Claim
137 words
A video signal format conversion apparatus, comprising: a memory for writing an input data by a first clock equal to a sampling rate of the input data and reading the input data by a second clock which is different from the first clock; a shift register which is coupled to the memory, and is driven by the second clock, wherein a shift operation is performed in each cycle of the second clock, and no signals other than the second clock are needed for the shift operation; a multiplication and summation circuit which is coupled to the shift register for cyclically multiplying each of a plurality of data output from the shift register by a factor utilizing pipeline processing synchronous with the second clock, thereby calculating a sum of values obtained by the multiplication by the second clock.
Claim 3
Dependent Claim
81 words
A video signal format conversion apparatus according to claim 1, wherein the multiplication and summation circuit includes: a factor register for storing the plurality of factors; a factor selector for selectively outputting the plurality of factors output from the factor register; a plurality of multipliers for multiplying the plurality of data output from the shift register by the respective factors output from the factor selector; and an adder for outputting the sum of the values output from the plurality of multipliers.
Claim 4
Dependent Claim
23 words
A video signal format conversion apparatus according to claim 2, wherein the adder generates a sum of three data output from the multipliers.
Claim 5
Dependent Claim
30 words
A video signal format conversion apparatus according to claim 2, further comprising a data selector for selectively supplying the multipliers with the plurality of data output from the shift register.
Claim 6
Dependent Claim
155 words
A video signal format conversion apparatus, comprising: a plurality of memories for writing an input data by a first clock equal to a sampling rate of the input data and reading the input data by a second clock which is different from the first clock; a line memory array for storing the data corresponding to one line read from the plurality of memories; a vertical direction operation circuit driven by the second clock for multiplying each of the plurality of signals output from the line memory array by a factor corresponding thereto among a plurality of factors in the vertical direction and summing values obtained by the multiplication; and a horizontal direction operation circuit driven by the second clock for multiplying each of a plurality of signals output from the vertical direction operation circuit by a factor corresponding thereto among a plurality of factors in the horizontal direction and summing values obtained by the multiplication.
Claim 7
Dependent Claim
155 words
A video signal format conversion apparatus, comprising: a plurality of memories for writing an input data by a first clock equal to a sampling rate of the input data and reading the input data by a second clock which is different from the first clock; a line memory array for storing the data corresponding to one line read from the plurality of memories; a vertical direction operation circuit driven by the second clock for multiplying each of the plurality of signals output from the line memory array by a factor corresponding thereto among a plurality of factors in the vertical direction and summing values obtained by the multiplication; and a horizontal direction operation circuit driven by the second clock for multiplying each of a plurality of signals output from the vertical direction operation circuit by a factor corresponding thereto among a plurality of factors in the horizontal direction and summing values obtained by the multiplication.
Claim 8
Dependent Claim
48 words
A video signal format conversion apparatus according to claim 5, wherein the line memory array includes: a plurality of selectors for selectively outputting a plurality of signals output from the plurality of memories; and a plurality of delay circuits for delaying the signals output from the respective selectors.
Claim 9
Dependent Claim
78 words
A video signal format conversion apparatus according to claim 6, wherein the vertical direction operation circuit includes: a factor register for storing the plurality of factors; a factor selector for selectively outputting the plurality of factors; a plurality of multipliers for respectively multiplying the plurality of data output from the line memory array and the respective factors output from the factor selectors; and an adder for outputting the sum of the values output from the plurality of multipliers.
Claim 10
Dependent Claim
23 words
A video signal format conversion apparatus according to claim 7, wherein the adder generates a sum of three data output from the multipliers.
References Cited (Backward Citations)
EP0213912A2
Cited
US4802025A
Cited
JPH01194784A
Cited
US4872054A
Cited
US5243421A
Cited
US5182633A
Cited
US5331346A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-16 | 2001-08-18 | 2002-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-16 | 2005-08-18 | 2006-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-16 | 2009-08-18 | 2010-02-17 | $7700.00 | Window Closed / Lapsed |