US5715467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Event driven power management control circuit and method therefor
Assignee: NXP BV
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Filing: 1996-04-04
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Granted: 1998-02-03
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Expires: 2016-04-04
Abstract
Abstract An event driven power management control system. The event driven power management control system is compatible with existing CPU power management control units which only monitor CPU activity. The event driven power management control system is able to modify a STPCLK# signal asserted by the CPU power management control unit if external or internal events in the computer system require the CPU to run at full speed in order to service the break event.
Inventors
- 👤 James J. Jirgal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:25
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3293; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
121 words
An event driven power management control circuit for a computer system comprising, in combination: Central Processing Unit (CPU) means for controlling operation of said computer system; CPU power management control means having an output coupled to said CPU means for sending a stop clock (STPCLK#) signal to said CPU means to activate and deactivate an internal clock of said CPU means based on activity of said CPU means; and system power management control means having an input coupled to said CPU power management control means and an output coupled to said CPU means for sampling said STPCLK# signal at timed intervals and for modifying said STPCLK# signal from said CPU power management control means based on activity of said computer system.
Claim 2
Dependent Claim
121 words
An event driven power management control circuit for a computer system comprising, in combination: Central Processing Unit (CPU) means for controlling operation of said computer system; CPU power management control means having an output coupled to said CPU means for sending a stop clock (STPCLK#) signal to said CPU means to activate and deactivate an internal clock of said CPU means based on activity of said CPU means; and system power management control means having an input coupled to said CPU power management control means and an output coupled to said CPU means for sampling said STPCLK# signal at timed intervals and for modifying said STPCLK# signal from said CPU power management control means based on activity of said computer system.
Claim 3
Dependent Claim
98 words
An event driven power management control circuit in accordance with claim 1 wherein said system power management control means comprises: stop clock logic means for modifying said signal from said CPU power management control means based on activity of said computer system; sampler means coupled to said stop clock logic means for sampling said signal from said CPU power management control means and for relaying said signal to said stop clock logic means; and timer means coupled to said sampler means for signalling said sampler means when to sample said signal from said CPU power management control means.
Claim 4
Dependent Claim
57 words
An event driven power management control circuit in accordance with claim 2 wherein said stop clock logic means further comprises means for monitoring external and internal events of said computer system for said stop clock logic means to modify said signal from said CPU power management control means based on said external events and said internal events.
Claim 5
Dependent Claim
34 words
An event driven power management control circuit in accordance with claim 1 wherein said CPU power management control means monitors a CPU control bus and a CPU address bus for activity of said CPU.
Claim 6
Dependent Claim
35 words
An event driven power management control circuit in accordance with claim 2 wherein said timer means is programmed with a time length approximately equal to a longest time requirement of a break event service routine.
Claim 7
Dependent Claim
231 words
An event driven power management control circuit for a computer system comprising, in combination: Central Processing Unit (CPU) means for controlling operation of said computer system; CPU power management control means having an output coupled to said CPU means for sending a signal to said CPU means to activate and deactivate an internal clock of said CPU means based on activity of said CPU means; and system power management control means having an input coupled to said CPU power management control means and an output coupled to said CPU means for modifying said signal from said CPU power management control means based on activity of said computer system, said system power management means comprising: stop clock logic means for monitoring external and internal events of said computer system and for modifying said signal from said CPU power management control means based on said external and internal events of said computer system; sampler means coupled to said stop clock logic means for sampling said signal from said CPU power management and for re means and for relaying said signal to said stop clock logic means; and timer means coupled to said sampler means for signalling said sampler means when to sample said signal from said CPU power management control means, said timer means being programmed with a time length approximately equal to a longest time requirement of a break event service routine.
Claim 8
Dependent Claim
231 words
An event driven power management control circuit for a computer system comprising, in combination: Central Processing Unit (CPU) means for controlling operation of said computer system; CPU power management control means having an output coupled to said CPU means for sending a signal to said CPU means to activate and deactivate an internal clock of said CPU means based on activity of said CPU means; and system power management control means having an input coupled to said CPU power management control means and an output coupled to said CPU means for modifying said signal from said CPU power management control means based on activity of said computer system, said system power management means comprising: stop clock logic means for monitoring external and internal events of said computer system and for modifying said signal from said CPU power management control means based on said external and internal events of said computer system; sampler means coupled to said stop clock logic means for sampling said signal from said CPU power management and for re means and for relaying said signal to said stop clock logic means; and timer means coupled to said sampler means for signalling said sampler means when to sample said signal from said CPU power management control means, said timer means being programmed with a time length approximately equal to a longest time requirement of a break event service routine.
Claim 9
Independent Claim
129 words
A method for providing an event driven power management control circuit for a computer system comprising the steps of: providing Central Processing Unit (CPU) means for controlling operation of said computer system; providing CPU power management control means having an output coupled to said CPU means for sending a stop clock (STPCLK#) signal to said CPU means to activate and deactivate an internal clock of said CPU means based on activity of said CPU means; and providing system power management control means having an input coupled to said CPU power management control means and an output coupled to said CPU means for sampling said STPCLK# signal at timed intervals and for modifying said STPCLK# signal from said CPU power management control means based on activity of said computer system.
Claim 10
Independent Claim
129 words
A method for providing an event driven power management control circuit for a computer system comprising the steps of: providing Central Processing Unit (CPU) means for controlling operation of said computer system; providing CPU power management control means having an output coupled to said CPU means for sending a stop clock (STPCLK#) signal to said CPU means to activate and deactivate an internal clock of said CPU means based on activity of said CPU means; and providing system power management control means having an input coupled to said CPU power management control means and an output coupled to said CPU means for sampling said STPCLK# signal at timed intervals and for modifying said STPCLK# signal from said CPU power management control means based on activity of said computer system.
Claim 11
Dependent Claim
101 words
The method of claim 7 wherein said step of providing system power management control means further comprises the steps of: providing stop clock logic means for modifying said signal from said CPU power management control means based on activity of said computer system; providing sampler means coupled to said stop clock logic means for sampling said signal from said CPU power management control means and for relaying said signal to said stop clock logic means; and providing timer means coupled to said sampler means for signalling said sampler means when to sample said signal from said CPU power management control means.
Claim 12
Dependent Claim
60 words
The method of claim 8 wherein said step of providing stop clock logic means further comprises the step of providing stop clock logic means having means for monitoring external and internal events of said computer system for said stop clock logic means to modify said signal from said system power management control means based on said external and internal events.
Claim 13
Dependent Claim
41 words
The method claim 7 wherein said step of providing CPU power management control means further comprises the step of coupling said CPU power management means to a CPU control bus and a CPU address bus to monitor activity of said CPU.
Claim 14
Dependent Claim
38 words
The method of claim 8 wherein said step of providing timer means further comprises the step of programming said timer means with a time length approximately equal to a longest time requirement of a break event service routine.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-02 | 2001-08-04 | 2002-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-02 | 2005-08-04 | 2006-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-02 | 2009-08-04 | 2010-02-03 | $7700.00 | Window Closed / Lapsed |