Interface circuit for supporting PCMCIA cards in an X-terminal

Claim 2

An interface circuit for supporting PCMCIA cards in an X-terminal, comprising: at least one PCMCIA card, said PCMCIA card being a PCMCIA memory card or a PCMCIA I/O card; a clock signal generator that outputs a clock signal; a main processor that outputs an address, a control signal, and a driving signal for reading and writing said PCMCIA card in accordance with said clock signal from said clock signal generator; a bus interface electrically connected with said main processor that outputs a bus operating signal in accordance with said driving signal from said main processor, outputs a command corresponding to said address and said control signal received from said main processor, and outputs a stop signal, thereby controlling data transmission from, and data reception by said main processor, said main processor and said PCMCIA card having different data access speeds, said bus interface outputting said bus operating signal in a first state, and outputting said stop signal in a second state, said bus interface controlling said first and second states in accordance with said different data access speeds, said bus interface including: an address decoder having an output unit for outputting a chip-selection signal which reads and writes a register of said PCMCIA card controller by interpreting said address from said main processor, said address decoder being adapted to output a memory window signal for reading and writing to said PCMCIA card when it is said PCMCIA memory card, and to output an I/O window signal to said PCMCIA card when it is said PCMCIA I/O card; a first state generator electrically connected with said output unit of said address decoder, said first state generator outputting a driving signal to operate said PCMCIA card controller during said first state according to a memory transaction start signal from said main processor; and a second state generator electrically connected with said output unit of said address decoder, said second state generator outputting a Data Ready signal during said second state for stopping said data transmission or said data reception operation of said PCMCIA card controller; and a PCMCIA card controller that inputs said address from said main processor in accordance with said bus operating signal from said bus interface, performs a Read/Write operation on said PCMCIA card in accordance with said command output from said bus interface, and stops a data reception or a data transmission operation based on said stop signal output from said bus interface.

Claim 3

The interface circuit as in claim 1, wherein said main processor has a faster access speed than said PCMCIA card, and wherein said bus interface controls said first and second states such that they provide a timing margin between said different data access speeds of said main processor and said PCMCIA card.

Claim 4

An interface circuit for supporting PCMCIA cards in an X-terminal, comprising: at least one PCMCIA card, said PCMCIA card being a PCMCIA memory card or a PCMCIA I/O card; a clock signal generator that outputs a clock signal; a main processor that outputs an address, a control signal, and a driving signal for reading and writing said PCMCIA card in accordance with said clock signal from said clock signal generator; a bus interface electrically connected with said main processor that outputs a bus operating signal in accordance with said driving signal from said main processor, outputs a command corresponding to said address and said control signal received from said main processor, and outputs a stop signal, thereby controlling a data transmission from, and data reception by said main processor, said bus interface comprising: an address decoder having an output unit for outputting a chip-selection signal which reads and writes a register of said PCMCIA card controller by interpreting said address from said main processor, said address decoder being adapted to output a memory window signal for reading and writing to said PCMCIA card when it is said PCMCIA memory card, and to output an I/O window signal to said PCMCIA card when it is said PCMCIA I/O card, a bus control signal generator electrically connected with said output unit of said address decoder, said bus control signal generating, in accordance with said control signal from said main processor, a first command for accessing said PCMCIA card when it is said PCMCIA memory card, and a second command for accessing said PCMCIA card when it is said PCMCIA I/O card, a first state generator electrically connected with said output unit of said address decoder, said first state generator outputting a driving signal to operate said PCMCIA card controller during said first state according to a memory transaction start signal from said main processor, and a second state generator electrically connected with said output unit of said address decoder, said second state generator outputting a Data Ready signal during said second state for stopping said data transmission or said data reception operation of said PCMCIA card controller; a PCMCIA card controller that inputs said address from said main processor in accordance with said bus operating signal from said bus interface, performs a Read/Write operation on said PCMCIA card in accordance with said command output from said bus interface, and stops a data reception or a data transmission operation based on said stop signal output from said bus interface.

Claim 5

An interface circuit for supporting PCMCIA cards in an X-terminal, comprising: at least one PCMCIA card, said PCMCIA card being a PCMCIA memory card or a PCMCIA I/O card; a clock signal generator that outputs a clock signal; a main processor that outputs an address, a control signal, and a driving signal for reading and writing said PCMCIA card in accordance with said clock signal from said clock signal generator; a bus interface electrically connected with said main processor that outputs a bus operating signal in accordance with said driving signal from said main processor, outputs a command corresponding to said address and said control signal received from said main processor, and outputs a stop signal, thereby controlling a data transmission from, and data reception by said main processor, said bus interface comprising: an address decoder having an output unit for outputting a chip-selection signal which reads and writes a register of said PCMCIA card controller by interpreting said address from said main processor, said address decoder being adapted to output a memory window signal for reading and writing to said PCMCIA card when it is said PCMCIA memory card, and to output an I/O window signal to said PCMCIA card when it is said PCMCIA I/O card, a bus control signal generator electrically connected with said output unit of said address decoder, said bus control signal generating, in accordance with said control signal from said main processor, a first command for accessing said PCMCIA card when it is said PCMCIA memory card, and a second command for accessing said PCMCIA card when it is said PCMCIA I/O card, a first state generator electrically connected with said output unit of said address decoder, said first state generator outputting a driving signal to operate said PCMCIA card controller during said first state according to a memory transaction start signal from said main processor, and a second state generator electrically connected with said output unit of said address decoder, said second state generator outputting a Data Ready signal during said second state for stopping said data transmission or said data reception operation of said PCMCIA card controller; a PCMCIA card controller that inputs said address from said main processor in accordance with said bus operating signal from said bus interface, performs a Read/Write operation on said PCMCIA card in accordance with said command output from said bus interface, and stops a data reception or a data transmission operation based on said stop signal output from said bus interface.