US5712688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video controller for displaying computer generated images on a television set
Assignee: Cirrus Logic Inc
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Filing: 1996-12-03
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Granted: 1998-01-27
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Expires: 2016-12-03
Abstract
Abstract In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.
Inventors
- 👤 Alexander J. Eglit
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:55
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; G; G09; G09G; G09G1/00; G09G1/28; G09G1/285; H04N21/00; H04N21/40; H04N21/41; H04N21/4104; H04N21/4113; H04N9/00; H04N9/64; H04N9/641
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
125 words
A video controller for enabling computer generated images to be displayed on a video monitor having a circuit for processing broadcast television signals, comprising: a state machine responsive to control circuitry of a computer for generating timing signals to define components of a video signal supplied to said video monitor to display said computer generated images, a delay circuit responsive to an output signal of said state machine for generating a control signal delayed by a variable delay time with respect to said output signal, said delay time being variable with horizontal lines, and a feedback circuit responsive to said control signal for controlling said state machine to generate a control component in said video signal to disable said circuit for processing broadcast television signals.
Claim 2
Dependent Claim
125 words
A video controller for enabling computer generated images to be displayed on a video monitor having a circuit for processing broadcast television signals, comprising: a state machine responsive to control circuitry of a computer for generating timing signals to define components of a video signal supplied to said video monitor to display said computer generated images, a delay circuit responsive to an output signal of said state machine for generating a control signal delayed by a variable delay time with respect to said output signal, said delay time being variable with horizontal lines, and a feedback circuit responsive to said control signal for controlling said state machine to generate a control component in said video signal to disable said circuit for processing broadcast television signals.
Claim 3
Dependent Claim
37 words
The controller of claim 1, wherein said delay circuit comprises a plurality of flip-flop circuits connected in series between a horizontal display enabling output of said state machine and a multiplexer controlled by a horizontal line count.
Claim 4
Dependent Claim
21 words
The controller of claim 2, wherein said multiplexer has a plurality of inputs respectively coupled to outputs of said flip-flop circuits.
Claim 5
Dependent Claim
23 words
The controller of claim 3 further comprising means for supplying said state machine and each of said flip-flop circuits with horizontal clock signals.
Claim 6
Dependent Claim
30 words
The controller of claim 4 further comprising means for disabling a horizontal clock input to said state machine in response to said horizontal display enabling output of said state machine.
Claim 7
Dependent Claim
27 words
The controller of claim 5 further comprising means for enabling said horizontal clock input to said state machine in response to an output signal of said multiplexer.
Claim 8
Dependent Claim
24 words
The controller of claim 6 wherein said state machine comprises means for generating a horizontal sync signal in response to said horizontal clock input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-26 | 2001-07-28 | 2002-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-26 | 2005-07-28 | 2006-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-26 | 2009-07-28 | 2010-01-27 | $7700.00 | Window Closed / Lapsed |