US5710783A
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Optimization of synchronization control in concatenated decoders
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-06-07
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Granted: 1998-01-20
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Expires: 2015-06-07
Abstract
Abstract A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions.
Inventors
- 👤 Daniel A. Luthi
- 👤 Nadav Ben-Efraim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:40
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H03; H03M; H03M13/00; H03M13/29; H03M13/33; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0611; H04L1/0045; H04L1/0054; H04L1/0064; H04L1/0065; H04L7/00; H04L7/04; H04L7/10
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
95 words
A method for synchronizing a decoder to a concatenated forward error correction coded digital signal, comprising the steps of: receiving a digitally encoded signal having concatenated forward error correction coding; synchronizing to a first layer of the concatenated forward error correction coded signal; synchronizing to a second layer of the concatenated forward error correction coded signal; and disabling the first layer synchronization when the second layer is synchronized to so that the second layer synchronization determines synchronization of the decoder for both the first and second layers of the forward error correction coded digital signal.
Claim 2
Independent Claim
95 words
A method for synchronizing a decoder to a concatenated forward error correction coded digital signal, comprising the steps of: receiving a digitally encoded signal having concatenated forward error correction coding; synchronizing to a first layer of the concatenated forward error correction coded signal; synchronizing to a second layer of the concatenated forward error correction coded signal; and disabling the first layer synchronization when the second layer is synchronized to so that the second layer synchronization determines synchronization of the decoder for both the first and second layers of the forward error correction coded digital signal.
Claim 3
Independent Claim
146 words
A method for synchronizing a decoder to a concatenated forward error correction coded digital signal, comprising the steps of: receiving a digitally encoded signal having concatenated forward error correction coding; synchronizing to a first layer of the concatenated forward error correction coded signal; synchronizing to a second layer of the concatenated forward error correction coded signal; synchronizing to a third layer of the concatenated forward error correction coded signal; disabling the first layer synchronization when the second layer is synchronized to so that the second layer synchronization determines synchronization of the decoder for both the first and second layers of the forward error correction coded digital signal; and disabling the second layer synchronization when the third layer is synchronized to so that the third layer synchronization determines synchronization of the decoder for the first, second and third layers of the forward error correction coded digital signal.
Claim 4
Independent Claim
146 words
A method for synchronizing a decoder to a concatenated forward error correction coded digital signal, comprising the steps of: receiving a digitally encoded signal having concatenated forward error correction coding; synchronizing to a first layer of the concatenated forward error correction coded signal; synchronizing to a second layer of the concatenated forward error correction coded signal; synchronizing to a third layer of the concatenated forward error correction coded signal; disabling the first layer synchronization when the second layer is synchronized to so that the second layer synchronization determines synchronization of the decoder for both the first and second layers of the forward error correction coded digital signal; and disabling the second layer synchronization when the third layer is synchronized to so that the third layer synchronization determines synchronization of the decoder for the first, second and third layers of the forward error correction coded digital signal.
Claim 5
Dependent Claim
20 words
The method of claim 2, wherein the step of synchronizing to the first layer is performed by a Viterbi synchronizer.
Claim 6
Dependent Claim
90 words
The method of claim 2, wherein the decoder includes a first stage for converting the concatenated forward error correction coded digital signal to a demodulated digital signal, wherein the decoder also includes a second stage for converting the demodulated digital signal into a scrambled signal, wherein the decoder further includes a third stage for converting the scrambled signal into a user signal, and wherein the method further comprises the step of determining when the second layer synchronization is in false lock by observing whether the third stage is in sync.
Claim 7
Dependent Claim
21 words
The method of claim 2, wherein the digital signal is a digital video signal having an MPEG-2 system layer document format.
Claim 8
Dependent Claim
98 words
The method of claim 2, wherein the decoder includes a first stage for converting the concatenated forward error correction coded digital signal to a demodulated digital signal, wherein the decoder also includes a second stage for converting the demodulated digital signal into a scrambled signal, wherein the decoder further includes a third stage for converting the scrambled signal into a user signal, and wherein the step of synchronizing to the third layer is performed with a Descrambler synchronizer which identifies an inverted sync word in the scrambled signal for determining synchronization of the third stage of the decoder.
Claim 9
Dependent Claim
18 words
The method of claim 6, wherein the inverted sync word occurs once every 8*N second layer code words.
Claim 10
Dependent Claim
81 words
The method of claim 2, wherein the decoder includes a first stage for converting the concatenated forward error correction coded digital signal to a demodulated digital signal, wherein the decoder also includes a second stage for converting the demodulated digital signal into a scrambled signal, and wherein the step of synchronizing to the second layer is performed by a Reed-Solomon synchronizer which identifies a sync word in the demodulated digital signal for determining synchronization of the second stage of the decoder.
Claim 11
Dependent Claim
19 words
The method of claim 8, further comprising the step of resolving signal phase ambiguity in the demodulated digital signal.
Claim 12
Dependent Claim
30 words
The method of claim 9, wherein the step of resolving the signal phase ambiguity is performed by the Reed-Solomon synchronizer simultaneously monitoring for both the sync word and its complement.
Claim 13
Independent Claim
144 words
A method for decoding a concatenated forward error correction coded digital video signal, comprising the steps of: receiving a digital video signal having concatenated forward error correction coding; synchronizing to the received concatenated forward error correction coded digital video signal; decoding the digital video signal in a first decoder, the first decoder having a first signal output; synchronizing to the first signal from the output of the first decoder; deinterleaving the first signal; decoding the first signal in a second decoder, the second decoder having a second signal output; synchronizing to the second signal from the output of the second decoder; decoding the second signal in a third decoder, the third decoder having a third signal output; and disabling synchronization to the first signal when the second signal is in synchronization, wherein the second signal determines synchronization for both the first and second decoders.
Claim 14
Independent Claim
144 words
A method for decoding a concatenated forward error correction coded digital video signal, comprising the steps of: receiving a digital video signal having concatenated forward error correction coding; synchronizing to the received concatenated forward error correction coded digital video signal; decoding the digital video signal in a first decoder, the first decoder having a first signal output; synchronizing to the first signal from the output of the first decoder; deinterleaving the first signal; decoding the first signal in a second decoder, the second decoder having a second signal output; synchronizing to the second signal from the output of the second decoder; decoding the second signal in a third decoder, the third decoder having a third signal output; and disabling synchronization to the first signal when the second signal is in synchronization, wherein the second signal determines synchronization for both the first and second decoders.
Claim 15
Dependent Claim
36 words
The method of claim 11, further comprising the step of disabling synchronization to the second signal when the third signal is in synchronization, wherein the third signal determines synchronization for the first, second and third decoders.
Claim 16
Dependent Claim
40 words
The method of claim 11, further comprising the steps of: determining optimal signal synchronization; disabling non-optimal signal synchronization; and utilizing the optimal signal synchronization for decoding the first, second and third signals in the first, second and third decoders, respectively.
Claim 17
Dependent Claim
13 words
The method of claim 11, wherein the first decoder is a Viterbi decoder.
Claim 18
Dependent Claim
13 words
The method of claim 11, wherein the second decoder is a Reed-Solomon decoder.
Claim 19
Dependent Claim
13 words
The method of claim 11, wherein the third decoder is a Descrambler decoder.
Claim 20
Independent Claim
110 words
An apparatus for synchronizing a decoder to a concatenated forward error correction coded digital signal, comprising: a first synchronizing circuit that synchronizes a first decoder to a first layer of the concatenated forward error correction coded signal; a second synchronizing circuit that synchronizes a second decoder to a second layer of the concatenated forward error correction coded signal; and a third synchronizing circuit that synchronizes a third decoder to a third layer of the concatenated forward error correction coded signal; said second synchronizing circuit disabling said first synchronizing circuit when the second layer is synchronized to, wherein the second synchronizing circuit determines synchronization for both the first and second decoders.
Claim 21
Independent Claim
110 words
An apparatus for synchronizing a decoder to a concatenated forward error correction coded digital signal, comprising: a first synchronizing circuit that synchronizes a first decoder to a first layer of the concatenated forward error correction coded signal; a second synchronizing circuit that synchronizes a second decoder to a second layer of the concatenated forward error correction coded signal; and a third synchronizing circuit that synchronizes a third decoder to a third layer of the concatenated forward error correction coded signal; said second synchronizing circuit disabling said first synchronizing circuit when the second layer is synchronized to, wherein the second synchronizing circuit determines synchronization for both the first and second decoders.
Claim 22
Dependent Claim
14 words
The apparatus of claim 17, wherein said first synchronizing circuit is a Viterbi synchronizer.
Claim 23
Dependent Claim
33 words
The apparatus of claim 17, wherein said second synchronizing circuit is a Reed-Solomon synchronizer which identifies a sync word in an output of said first decoder for determining synchronization of said second decoder.
Claim 24
Dependent Claim
34 words
The apparatus of claim 17, wherein said third synchronizing circuit is a Descrambler synchronizer which identifies an inverted sync word in an output of said second decoder for determining synchronization of said third decoder.
Claim 25
Independent Claim
128 words
An apparatus for decoding a concatenated forward error correction coded digital video signal, comprising: a first decoder having a first signal output; a first synchronizing circuit that synchronizes said first decoder to the concatenated forward error correction coded digital video signal; a second decoder having a second signal output; a second synchronizing circuit that synchronizes said second decoder to the first signal from the output of said first decoder; a third decoder having a third signal output; a third synchronizing circuit that synchronizes said third decoder to the second signal from the output of said second decoder; and said second synchronizing circuit disabling said first synchronizing circuit when said second decoder is synchronized, wherein the second synchronizing circuit determines synchronization for both of said first and second decoders.
Claim 26
Independent Claim
128 words
An apparatus for decoding a concatenated forward error correction coded digital video signal, comprising: a first decoder having a first signal output; a first synchronizing circuit that synchronizes said first decoder to the concatenated forward error correction coded digital video signal; a second decoder having a second signal output; a second synchronizing circuit that synchronizes said second decoder to the first signal from the output of said first decoder; a third decoder having a third signal output; a third synchronizing circuit that synchronizes said third decoder to the second signal from the output of said second decoder; and said second synchronizing circuit disabling said first synchronizing circuit when said second decoder is synchronized, wherein the second synchronizing circuit determines synchronization for both of said first and second decoders.
Claim 27
Dependent Claim
36 words
The apparatus of claim 21, further comprising said third synchronizing circuit disabling said second synchronizing circuit when said third decoder is synchronized, wherein the third synchronizing circuit determines synchronization for said first, second and third decoders.
Claim 28
Dependent Claim
41 words
The apparatus of claim 21, further comprising logic circuits for choosing an optimal synchronizing circuit for a given signal condition and disabling the other synchronizing circuits, wherein the chosen optimal synchronizing circuit determines synchronization of the respective signals to the decoders.
Claim 29
Dependent Claim
19 words
The apparatus of claim 21, further comprising a deinterleaving circuit between said second synchronizing circuit and said second decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-19 | 2001-07-21 | 2002-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-19 | 2005-07-21 | 2006-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-19 | 2009-07-21 | 2010-01-20 | $7700.00 | Window Closed / Lapsed |