US5708665A
Expired / Lapsed
US
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Digital receiver using equalization and block decoding with erasure and error correction
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-08-22
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Granted: 1998-01-13
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Expires: 2016-08-22
Abstract
Abstract A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.
Inventors
- 👤 Daniel A. Luthi
- 👤 Ravi Bhaskaran
- 👤 Dojun Rhee
- 👤 Advait M. Mogre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:37
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H04L1/0045; H04L1/0064; H04L1/0065; H04L1/20; H04L1/208
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
190 words
A communications system comprising: an encoder configured to receive a digital signal and thereafter convert said digital signal to a coded digital signal; a transmission channel through which said coded digital signal is transmitted; a decoder coupled to said transmission channel to receive said coded digital signal, configured to correct erasures and errors in said coded digital signal, and configured to thereafter convert said coded digital signal to substantially said digital signal; and an error detector configured to provide error flags to said decoder, said error detector comprising: a decision element coupled to receive an equalized coded digital signal and thereafter render a set of symbol decisions; a comparator with two inputs, first of said two inputs coupled to receive said equalized coded digital signal, and the second of said two inputs coupled to receive said set of symbol decisions; said comparator configured to produce a noise signal representing an estimated noise value; and a threshold detector coupled to receive an error signal which is indicative of an error burst in said coded digital sequence if a function of said signal exceeds a threshold, and thereafter assert an error flag.
Claim 2
Dependent Claim
190 words
A communications system comprising: an encoder configured to receive a digital signal and thereafter convert said digital signal to a coded digital signal; a transmission channel through which said coded digital signal is transmitted; a decoder coupled to said transmission channel to receive said coded digital signal, configured to correct erasures and errors in said coded digital signal, and configured to thereafter convert said coded digital signal to substantially said digital signal; and an error detector configured to provide error flags to said decoder, said error detector comprising: a decision element coupled to receive an equalized coded digital signal and thereafter render a set of symbol decisions; a comparator with two inputs, first of said two inputs coupled to receive said equalized coded digital signal, and the second of said two inputs coupled to receive said set of symbol decisions; said comparator configured to produce a noise signal representing an estimated noise value; and a threshold detector coupled to receive an error signal which is indicative of an error burst in said coded digital sequence if a function of said signal exceeds a threshold, and thereafter assert an error flag.
Claim 3
Dependent Claim
31 words
The communications system as recited in claim 1, wherein said decoder further comprises a de-interleaver operably coupled to the output of the transmission channel and the input of an outer decoder.
Claim 4
Dependent Claim
40 words
The communications system as recited in claim 2, wherein the output of said error detector is coupled to said de-interleaver such that said error flag remains attributed to a location in which an error appears in said coded digital signal.
Claim 5
Dependent Claim
18 words
The communications system as recited in claim 3, wherein said transmission channel capable of being a shielded cable.
Claim 6
Dependent Claim
46 words
The communications system as recited in claim 3, wherein said error detector further comprises: a windowing filter interposed between said comparator and said threshold detector, said windowing filter configured to produce said error signal by summing a fixed number of past samples of said noise signal.
Claim 7
Dependent Claim
30 words
The communications system as recited in claim 5, wherein said error detector further comprises: an equalizer coupled to receive said coded digital signal and thereafter produce said equalized digital signal.
Claim 8
Independent Claim
163 words
An apparatus for detecting errors within a decoded sequence of symbols, comprising: a decoder configured to receive a coded digital signal, configured to correct erasures and errors in said coded digital signal, and configured to thereafter convert said coded digital signal to a digital signal; and an error detector configured to provide error flags to said decoder, said error detector comprising: a decision element coupled to receive an equalized coded digital signal and thereafter render a set of symbol decisions; a comparator with two inputs, first of said two inputs coupled to receive said equalized coded digital signal, and the second of said two inputs coupled to receive said set of symbol decisions; said comparator configured to produce a noise signal representing an estimated noise value; and a threshold detector coupled to receive an error signal which is indicative of an error burst in said coded digital sequence if a function of said signal exceeds a threshold, and thereafter assert an error flag.
Claim 9
Independent Claim
163 words
An apparatus for detecting errors within a decoded sequence of symbols, comprising: a decoder configured to receive a coded digital signal, configured to correct erasures and errors in said coded digital signal, and configured to thereafter convert said coded digital signal to a digital signal; and an error detector configured to provide error flags to said decoder, said error detector comprising: a decision element coupled to receive an equalized coded digital signal and thereafter render a set of symbol decisions; a comparator with two inputs, first of said two inputs coupled to receive said equalized coded digital signal, and the second of said two inputs coupled to receive said set of symbol decisions; said comparator configured to produce a noise signal representing an estimated noise value; and a threshold detector coupled to receive an error signal which is indicative of an error burst in said coded digital sequence if a function of said signal exceeds a threshold, and thereafter assert an error flag.
Claim 10
Dependent Claim
30 words
The apparatus as recited in claim 7, wherein said decoder further comprises a de-interleaver operably coupled to the output of the transmission channel and the input of an outer decoder.
Claim 11
Dependent Claim
39 words
The apparatus as recited in claim 8, wherein the output of said error detector is coupled to said de-interleaver such that said error flag remains attributed to a location in which an error appears in said coded digital signal.
Claim 12
Dependent Claim
39 words
The apparatus as recited in claim 9, wherein said error detector further comprises: a windowing filter interposed between said comparator and said threshold detector, said windowing filter configured to produce said error signal by operating on said noise signal.
Claim 13
Dependent Claim
29 words
The apparatus as recited in claim 10, wherein said error detector further comprises: an equalizer coupled to receive said coded digital signal and thereafter produce said equalized digital signal.
Claim 14
Dependent Claim
41 words
The apparatus as recited in claim 10, wherein said flag is set in each of multiple locations within a region of said coded digital signal corresponding to intervals in which values of said function of the error signal exceed said threshold.
Claim 15
Dependent Claim
37 words
The apparatus as recited in claim 12, wherein said multiple locations are adjacent within said coded digital signal prior to entry into said de-interleaver and are separated within said coded digital signal after exit from said de-interleaver.
Claim 16
Dependent Claim
36 words
The apparatus as recited in claim 13, wherein said flag may be set in multiple locations of a code word at approximately twice the quantity of erroneous symbols correctable by an apparatus absent said error detector.
References Cited (Backward Citations)
US4829525A
Cited
US5430743A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-12 | 2001-07-14 | 2002-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-12 | 2005-07-14 | 2006-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-12 | 2009-07-14 | 2010-01-13 | $7700.00 | Window Closed / Lapsed |