US5706481A
Expired / Lapsed
US
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Apparatus and method for integrating texture memory and interpolation logic in a computer system
Assignee: Microsoft Technology Licensing LLC
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Filing: 1996-05-22
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Granted: 1998-01-06
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Expires: 2016-05-22
Abstract
Abstract In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.
Inventors
- 👤 Marc R. Hannah
- 👤 Michael B. Nagy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:40
CPC Classifications
G; G06; G06T; G06T15/00; G06T15/04; G06T11/00; G06T11/10; G06T15/005
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
93 words
A computer system having semiconductor chip for performing texture mapping, said semiconductor chip comprising: an input configured to input texture mappings to said semiconductor chip; a cache memory coupled to said input, said cache memory configured to store texture mapping data; an interpolator coupled to said cache memory for producing an output rendered pixel by interpolating from a texture mapping stored in said cache memory; and an output coupled to said interpolator for outputting said output rendered pixel, wherein said input, said cache memory, and said interpolator reside on a single substrate device.
Claim 2
Dependent Claim
93 words
A computer system having semiconductor chip for performing texture mapping, said semiconductor chip comprising: an input configured to input texture mappings to said semiconductor chip; a cache memory coupled to said input, said cache memory configured to store texture mapping data; an interpolator coupled to said cache memory for producing an output rendered pixel by interpolating from a texture mapping stored in said cache memory; and an output coupled to said interpolator for outputting said output rendered pixel, wherein said input, said cache memory, and said interpolator reside on a single substrate device.
Claim 3
Dependent Claim
66 words
The computer system of claim 1, further including a main memory, coupled to said interpolator, said main memory is external to said semiconductor chip and is configured to store texture mappings; and a memory controller coupled to said cache memory and said main memory, said memory controller configured to perform memory access cycles to said main memory in parallel with read cycles to said cache memory.
Claim 4
Dependent Claim
29 words
The computer system of claim 2, wherein said main memory and said cache memory are divided into at least two independently addressable banks to decouple loading and resampling operations.
Claim 5
Dependent Claim
43 words
The computer system of claim 3, wherein said semiconductor chip includes a fault predicting device residing on said substrate, said fault predicting device configured to predict faults by determining data that will be required and fetching said data before said data is required.
Claim 6
Dependent Claim
27 words
The computer system of claim 4, wherein the interpolator includes of a plurality of modular slices configured to be stacked to generate interpolations for different data widths.
Claim 7
Dependent Claim
27 words
The computer system of claim 5, wherein said interpolator is configured to perform a nearest neighbor selection of a texture mapping to produce said output rendered pixel.
Claim 8
Dependent Claim
26 words
The computer system of claim 6, wherein said interpolator is configured to perform a bi-linear interpolation of a texture mapping to produce said output rendered pixel.
Claim 9
Dependent Claim
38 words
The computer system of claim 9, wherein said semiconductor chip further includes a filter device coupled to said input, said filter device configured to filter a texture mapping prior to storing said texture mapping in said cache memory.
Claim 10
Dependent Claim
17 words
The computer system of claim 8, wherein said filter device is comprised of a 2×2 box filter.
Claim 11
Independent Claim
60 words
A method for performing texture mapping, said method comprising the steps of: storing texture mapping data on a cache memory residing on a semiconductor chip; producing an output rendered pixel via an interpolator interpolating from a texture mapping stored in said cache memory, said interpolator residing on said semiconductor chip; and outputting said output rendered pixel from said semiconductor chip.
Claim 12
Independent Claim
60 words
A method for performing texture mapping, said method comprising the steps of: storing texture mapping data on a cache memory residing on a semiconductor chip; producing an output rendered pixel via an interpolator interpolating from a texture mapping stored in said cache memory, said interpolator residing on said semiconductor chip; and outputting said output rendered pixel from said semiconductor chip.
Claim 13
Dependent Claim
32 words
The method of claim 10, further including the step of performing memory access cycles to a main memory, external to said semiconductor chip, in parallel with read cycles to said cache memory.
Claim 14
Dependent Claim
31 words
The method of claim 11, further including the step of dividing said main memory and said cache memory into at least two independently addressable banks to decouple loading and resampling operations.
Claim 15
Dependent Claim
42 words
The method of claim 12, further including the step of predicting faults via a first device residing on said semiconductor chip, wherein said faults are predicted by determining data that will be required and fetching said data before said data is required.
Claim 16
Dependent Claim
25 words
The method of claim 13, wherein the interpolator includes a plurality of modular slices configured to be stacked to generate interpolations for different data widths.
Claim 17
Dependent Claim
27 words
The method of claim 14, further including the step of said interpolator performing a nearest neighbor selection of a texture mapping to produce said output rendered pixel.
Claim 18
Dependent Claim
26 words
The method of claim 15, further including the step of said interpolator performing a bi-linear interpolation of a texture mapping to produce said output rendered pixel.
Claim 19
Dependent Claim
24 words
The method of claim 16, further including the step of filtering a texture mapping prior to storing said texture mapping in said cache memory.
Claim 20
Dependent Claim
15 words
The method of claim 17, wherein said filtering is performed utilizing a 2×2 box filter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-05 | 2001-07-07 | 2002-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-05 | 2005-07-07 | 2006-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-05 | 2009-07-07 | 2010-01-06 | $7700.00 | Window Closed / Lapsed |