Joint maximum likelihood channel and timing error estimation

Claim 2

In a system in which an incoming signal is received into a receiver with unknown multipath interference and timing error, the incoming signal being divided into time frames, and each time frame including a known portion, a method of jointly determining an initial channel tap estimate for a maximum likelihood sequence estimating equalizer and a timing error of the incoming signal, the method comprising: receiving the incoming signal into the receiver; locating the known portion within a time frame of the incoming signal in response to a clock signal generated within the receiver; comparing the known portion having been located with a stored representation of the known portion; comparing the known portion having been located with a stored representation of a derivative of the known portion; determining jointly, the initial channel tap estimates and the timing error of the incoming signal with respect to the clock signal in response to the comparing with the stored representation of the known portion and the comparing with the stored representation of the derivative of the known portion; and locating a subsequent known portion within a subsequent time frame of the incoming signal in response to the clock signal generated within the receiver and in response to the timing error having been determined.

Claim 3

The method of claim 1 including filtering the timing error having been determined using an infinite impulse response filter.

Claim 4

The method of claim 1 wherein said locating of said subsequent known portion includes: advancing said clock signal in the event said timing error is positive; and retarding said clock signal in the event said timing error is negative.

Claim 5

The method of claim 1 wherein said locating of said known portion within said time frame of said incoming signal includes locating a synch pattern within said time frame of said incoming signal, and wherein said locating of said subsequent known portion within said subsequent time frame of said incoming signal includes locating a subsequent synch pattern within said subsequent time frame of said incoming signal.

Claim 6

The method of claim 4 wherein said receiving of said incoming signal includes receiving a remainder portion of said incoming signal within said time frame of said incoming signal.

Claim 7

The method of claim 5 further comprising: transmitting, before said receiving of said incoming signal into said receiver, said incoming signal through a communications channel from a transmitter to said receiver.

Claim 8

The method of claim 6 wherein said transmitting includes transmitting said known portion during said time frame of said incoming signal and transmitting said subsequent known portion during said subsequent time frame of said incoming signal, said known portion of said incoming signal and said subsequent known portion of said incoming signal being transmitted as substantially identical portions of said incoming signal.

Claim 9

The method of claim 7 further comprising: distorting, before said receiving of said incoming signal into said receiver, said incoming signal using said communications channel.

Claim 10

The method of claim 8 wherein said transmitting includes transmitting said incoming signal through air.

Claim 11

The method of claim 9 further comprising: demodulating said remainder portion of said incoming signal.

Claim 12

The method of claim 5 including: communicating the initial channel tap estimates to a maximum likelihood sequence estimating equalizer.

Claim 13

The method of claim 1 wherein said determining, jointly, said initial channel tap estimates and said timing error includes determining ##EQU16## wherein Λ(τ) is a likelihood ratio and τ is said timing error in said incoming signal relative to said clock signal.

Claim 14

In a system comprising a clock circuit that generates a clock signal, and a receiver that receives an incoming signal with multipath interference and an unknown timing error relative to the clock signal, the incoming signal being divided into time frames, and each time frame including a known portion, an improvement comprising: coarse acquisition means for locating the known portion within a time frame of the incoming signal, the locating means being coupled to the clock circuit and the locating being in response to the clock signal generated by the clock circuit; memory means for storing a representation of the known portion, and for storing a representation of a derivative of the known portion; processor means coupled to the coarse acquisition means and to the memory means, the processor means being for comparing the known portion, having been located by the coarse acquisition means, with the representation of the known portion, and for comparing the known portion, having been located by the coarse acquisition means, with a stored representation of a derivative of the known portion; determining means for jointly determining initial tap coefficients for a maximum likelihood sequence estimating equalizer and the timing error of the incoming signal with respect to the clock signal in response to the processor means; and clock adjusting means for locating a subsequent known portion within a subsequent time frame of the incoming signal in response to the clock signal generated by the clock circuit and in response to the timing error having been determined by the determining means.

Claim 15

In a system comprising a clock circuit that generates a clock signal, and a receiver that receives an incoming signal with multipath interference and an unknown timing error relative to the clock signal, the incoming signal being divided into time frames, and each time frame including a known portion, an improvement comprising: coarse acquisition means for locating the known portion within a time frame of the incoming signal, the locating means being coupled to the clock circuit and the locating being in response to the clock signal generated by the clock circuit; memory means for storing a representation of the known portion, and for storing a representation of a derivative of the known portion; processor means coupled to the coarse acquisition means and to the memory means, the processor means being for comparing the known portion, having been located by the coarse acquisition means, with the representation of the known portion, and for comparing the known portion, having been located by the coarse acquisition means, with a stored representation of a derivative of the known portion; determining means for jointly determining initial tap coefficients for a maximum likelihood sequence estimating equalizer and the timing error of the incoming signal with respect to the clock signal in response to the processor means; and clock adjusting means for locating a subsequent known portion within a subsequent time frame of the incoming signal in response to the clock signal generated by the clock circuit and in response to the timing error having been determined by the determining means.