US5706156A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having an ESD protective circuitry
Assignee: PS4 Luxco SARL
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Filing: 1996-01-25
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Granted: 1998-01-06
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Expires: 2016-01-25
Abstract
Abstract A semiconductor device has a protective circuitry including a common discharge line, a first protective device connected between one of input/output terminals and the discharge line, and a second protective device connected between one of Vcc and ground terminals and the discharge line. The second protective device has an on-resistance as much as 1/2 of the on-resistance of the first protective device. Each of the power terminals and ground terminals generally has a large capacitance to accumulate a large amount of electric charge during a CDM test after charging of the semiconductor device as a whole. The low on-resistance prevents the inner circuit and input/output buffers of the semiconductor device from being applied with a higher potential during subsequent grounding of the semiconductor device in the CDM test.
Inventors
- 👤 Kaoru Narita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:54
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/611; H10D89/711
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
124 words
A semiconductor device, comprising: a substrate; an inner circuit formed on said substrate; an external terminal group disposed for said inner circuit and including a plurality of first terminals and a plurality of second terminals; and a protective circuitry including: a common discharge line; a first protective device connected between each of said first terminals and said common discharge line; and a second protective device connected between each of said second terminals and said common discharge line, each of said first terminals having a first parasitic capacitance, each of said second terminals having a second parasitic capacitance larger than said first parasitic capacitance, said first protective device having a first on-resistance, said second protective device having a second on-resistance smaller than said first on-resistance.
Claim 2
Dependent Claim
124 words
A semiconductor device, comprising: a substrate; an inner circuit formed on said substrate; an external terminal group disposed for said inner circuit and including a plurality of first terminals and a plurality of second terminals; and a protective circuitry including: a common discharge line; a first protective device connected between each of said first terminals and said common discharge line; and a second protective device connected between each of said second terminals and said common discharge line, each of said first terminals having a first parasitic capacitance, each of said second terminals having a second parasitic capacitance larger than said first parasitic capacitance, said first protective device having a first on-resistance, said second protective device having a second on-resistance smaller than said first on-resistance.
Claim 3
Dependent Claim
32 words
A semiconductor device as defined in claim 1 wherein said first terminals include a plurality of input/output terminals and said second terminals include at least one of power terminals and ground terminals.
Claim 4
Dependent Claim
37 words
A semiconductor device as defined in claim 1 wherein said second protective device includes a plurality of protective elements each having a current path substantially equal to a current path of said first protective device in width.
Claim 5
Dependent Claim
29 words
A semiconductor device according to claim 1, wherein said second protective device has an on-resistance no more than 1/2 as much as the on-resistance of said first protective device.
Claim 6
Dependent Claim
21 words
A semiconductor device as defined in claim 1 wherein each of said first and second protective devices includes a clamp element.
Claim 7
Dependent Claim
16 words
A semiconductor device as defined in claim 5 wherein said clamp element comprises a bipolar transistor.
Claim 8
Dependent Claim
15 words
A semiconductor device as defined in claim 5 wherein said clamp element comprises a thyristor.
Claim 9
Dependent Claim
16 words
A semiconductor device as defined in claim 5 wherein said clamp element comprises a NMOS FET.
Claim 10
Dependent Claim
28 words
A semiconductor device as defined in claim 5 wherein each of said first and second protective devices further includes a diode connected in parallel to said clamp element.
Claim 11
Dependent Claim
127 words
A protective circuitry for a semiconductor device including a substrate, an inner circuit formed on said substrate, an external terminal group disposed for said inner circuit and including a plurality of first terminals and a plurality of second terminals, said protective circuitry comprising: a common discharge line; a first protective device connected between each of said first terminals and said common discharge line; and a second protective device connected between each of said second terminals and said common discharge line, each of said first terminals having a first parasitic capacitance, each of said second terminals having a second parasitic capacitance larger than said first parasitic capacitance, said first protective device having a first on-resistance, said second protective device having a second on-resistance smaller than said first on-resistance.
Claim 12
Dependent Claim
127 words
A protective circuitry for a semiconductor device including a substrate, an inner circuit formed on said substrate, an external terminal group disposed for said inner circuit and including a plurality of first terminals and a plurality of second terminals, said protective circuitry comprising: a common discharge line; a first protective device connected between each of said first terminals and said common discharge line; and a second protective device connected between each of said second terminals and said common discharge line, each of said first terminals having a first parasitic capacitance, each of said second terminals having a second parasitic capacitance larger than said first parasitic capacitance, said first protective device having a first on-resistance, said second protective device having a second on-resistance smaller than said first on-resistance.
Claim 13
Dependent Claim
31 words
A protective circuitry according to claim 10, wherein said first terminals include a plurality of input/output terminals and said second terminals include at least one of power terminals and ground terminals.
Claim 14
Dependent Claim
36 words
A protective circuitry according to claim 10, wherein said second protective device includes a plurality of protective elements each having a current path substantially equal to a current path of said first protective device in width.
Claim 15
Dependent Claim
29 words
A protective circuitry according to claim 10, wherein said second protective device has an on-resistance no more than 1/2 as much as the on-resistance of said first protective device.
Claim 16
Dependent Claim
20 words
A protective circuitry according to claim 10, wherein each of said first and second protective devices includes a clamp element.
Claim 17
Dependent Claim
15 words
A protective circuitry according to claim 14, wherein said clamp element comprises a bipolar transistor.
Claim 18
Dependent Claim
14 words
A protective circuitry according to claim 14, wherein said clamp element comprises a thyristor.
Claim 19
Dependent Claim
15 words
A protective circuitry according to claim 14, wherein said clamp element comprises a NMOS FET.
Claim 20
Dependent Claim
27 words
A protective circuitry according to claim 14, wherein each of said first and second protective devices further includes a diode connected in parallel to said clamp element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-05 | 2001-07-07 | 2002-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-05 | 2005-07-07 | 2006-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-05 | 2009-07-07 | 2010-01-06 | $7700.00 | Window Closed / Lapsed |