US5705320A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Recovery of alignment marks and laser marks after chemical-mechanical-polishing
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1996-11-12
•
Granted: 1998-01-06
•
Expires: 2016-11-12
Abstract
Abstract The preservation of alignment marks and identification marks throughout the multitude of processing steps employed for the manufacture of integrated circuit chips often requires the inclusion of additional operations which impact production cost and product throughput. Current increased utilization of global planarization operations such as chemical-mechanical-polishing have forced the inclusion of additional window opening lithographic steps requiring additional masks and etch operations to keep these marks from being obscured. This invention provides a technique and a reticle design for clearing and preserving alignment and wafer identification marks through planarization and metallization levels with improved throughput and without the need for additional reticles to clear the marks. The alignment mark areas are exposed by a large clear-out window located in the frame area of the contact/via reticle while the wafer identification marks are accommodated in the same fashion by the metal pattern reticle. The lithography for integrated circuit pattern exposure and the window exposure is accomplished by a single stepper pass at each level.
Inventors
- 👤 Shun-Liang Hsu
- 👤 Shih-Shiung Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:05
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70491; G03F7/70541; G03F7/70058; G03F7/70066; G03F7/70425; G03F7/70466; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076; H; H10; H10W; H10W46/00; H10W46/201
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
217 words
A method for patterning a planarized insulative layer on a semiconductor wafer, said semiconductor wafer having a plurality of integrated circuit dice and a plurality of dice containing alignment marks, comprising: (a) providing a semiconductor wafer having a plurality of integrated circuit dice and a plurality of dice containing alignment marks and having a planarized insulative layer over its surface; (b) depositing a photoresist layer; (c) mounting said semiconductor wafer on the stage of a stepper; (d) mounting a reticle in said stepper, said reticle having a photolithographic image of an integrated circuit pattern enclosed within a rectangular frame region and a window in said frame region; (e) aligning said semiconductor wafer to said alignment marks and exposing said photoresist layer over a first integrated circuit die with said photolithographic image; (f) stepping and exposing said photoresist layer over said integrated circuit dice with said photolithographic image in sequence until a die containing said alignment marks is reached; (h) making multiple overlapping exposures of said photoresist layer over said alignment marks through said window; (l) repeating steps (f) through (h) until all said integrated circuit dice and all said dice containing alignment marks have been exposed; (j) developing said photoresist layer; and (k) etching said insulative layer with a unidirectional etching technique, thereby exposing said alignment marks.
Claim 2
Independent Claim
217 words
A method for patterning a planarized insulative layer on a semiconductor wafer, said semiconductor wafer having a plurality of integrated circuit dice and a plurality of dice containing alignment marks, comprising: (a) providing a semiconductor wafer having a plurality of integrated circuit dice and a plurality of dice containing alignment marks and having a planarized insulative layer over its surface; (b) depositing a photoresist layer; (c) mounting said semiconductor wafer on the stage of a stepper; (d) mounting a reticle in said stepper, said reticle having a photolithographic image of an integrated circuit pattern enclosed within a rectangular frame region and a window in said frame region; (e) aligning said semiconductor wafer to said alignment marks and exposing said photoresist layer over a first integrated circuit die with said photolithographic image; (f) stepping and exposing said photoresist layer over said integrated circuit dice with said photolithographic image in sequence until a die containing said alignment marks is reached; (h) making multiple overlapping exposures of said photoresist layer over said alignment marks through said window; (l) repeating steps (f) through (h) until all said integrated circuit dice and all said dice containing alignment marks have been exposed; (j) developing said photoresist layer; and (k) etching said insulative layer with a unidirectional etching technique, thereby exposing said alignment marks.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein said window is rectangular with dimensions of about 3.5 mm by 1.6 mm.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein said integrated circuit pattern comprises contacts openings.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein said integrated circuit pattern comprises via openings.
Claim 6
Dependent Claim
29 words
The method of claim 1 wherein programmable mask blades are employed by said stepper during the performance of step (h) to expose said photoresist layer only through said window.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein said unidirectional etching technique is reactive-ion-etching.
Claim 8
Independent Claim
204 words
A method for patterning an opaque layer deposited over a semiconductor wafer, said semiconductor wafer having a plurality of integrated circuit dice, a plurality of dice containing alignment marks, and a peripheral region containing identification marks, comprising: (a) providing a semiconductor wafer having a plurality of integrated circuit dice, a plurality of dice containing alignment marks, and a peripheral region containing identification marks and having an opaque layer formed over its surface; (b) depositing a photoresist layer; (c) mounting said semiconductor wafer on the stage of a stepper; (d) mounting a reticle in said stepper, said reticle having a rectangular photolithographic image of an integrated circuit pattern surrounded by a rectangular frame region and a window within said frame region; (e) aligning and exposing a first integrated circuit die on said semiconductor wafer to said photolithographic image; (f) stepping and exposing successive integrated circuit dice to said photolithographic image in sequence, skipping dies containing alignment marks until all integrated circuit dice have been exposed; (g) stepping to said peripheral region; (h) making multiple overlapping exposures through said window until said photoresist layer over said identification marks is exposed; (l) developing said photoresist layer; and (j) etching said opaque layer, thereby revealing said identification marks.
Claim 9
Independent Claim
204 words
A method for patterning an opaque layer deposited over a semiconductor wafer, said semiconductor wafer having a plurality of integrated circuit dice, a plurality of dice containing alignment marks, and a peripheral region containing identification marks, comprising: (a) providing a semiconductor wafer having a plurality of integrated circuit dice, a plurality of dice containing alignment marks, and a peripheral region containing identification marks and having an opaque layer formed over its surface; (b) depositing a photoresist layer; (c) mounting said semiconductor wafer on the stage of a stepper; (d) mounting a reticle in said stepper, said reticle having a rectangular photolithographic image of an integrated circuit pattern surrounded by a rectangular frame region and a window within said frame region; (e) aligning and exposing a first integrated circuit die on said semiconductor wafer to said photolithographic image; (f) stepping and exposing successive integrated circuit dice to said photolithographic image in sequence, skipping dies containing alignment marks until all integrated circuit dice have been exposed; (g) stepping to said peripheral region; (h) making multiple overlapping exposures through said window until said photoresist layer over said identification marks is exposed; (l) developing said photoresist layer; and (j) etching said opaque layer, thereby revealing said identification marks.
Claim 10
Dependent Claim
19 words
The method of claim 7 wherein said window is rectangular with dimensions of about 3.5 mm by 1.6 mm.
Claim 11
Dependent Claim
12 words
The method of claim 7 wherein said opaque layer is a metal.
Claim 12
Dependent Claim
13 words
The method of claim 7 wherein said integrated circuit pattern comprises interconnection metallization.
Claim 13
Dependent Claim
29 words
The method of claim 7 wherein programmable mask blades are employed by said stepper during the performance of step (h) to expose said photoresist layer only through said window.
Claim 14
Dependent Claim
20 words
The method of claim 7 wherein said peripheral region is located adjacent to the flat edge of said semiconductor wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-05 | 2001-07-07 | 2002-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-05 | 2005-07-07 | 2006-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-05 | 2009-07-07 | 2010-01-06 | $7700.00 | Window Closed / Lapsed |