Semiconductor memory device having dual boosting circuits to reduce energy required to supply boosting voltages

Claim 2

A semiconductor memory device comprising: pairs of bit lines; first circuits which are respectively coupled to the pairs of bit lines and which precharge the pairs of bit lines and precharge the pairs of bit lines in accordance with a first control signal; sense amplifiers respectively coupled to the pairs of bit lines; second circuits which are respectively provided between the pairs of bit lines and the sense amplifiers and selectively connect the pairs of bit lines to the sense amplifiers in response to a second control signal; a third circuit which produces first and second boosted voltages from a power supply voltage and supplies the first and second boosted voltages to the first and second circuits respectively, wherein the first control signal is produced from the first boosted voltage and the second control signal is produced from the second boosted voltage, the first boosted voltage being lower than the second boosted voltage; and wherein the second control signal is applied to word lines in order to drive the word lines.

Claim 3

The semiconductor memory device as claimed in claim 1, wherein the third circuit comprises a first circuit section which derives the first boosted voltage from the power supply voltage, and a second circuit section which derives the second boosted voltage from the power supply voltage.

Claim 4

The semiconductor memory device as claimed in claim 2, wherein said first circuit section comprises: a first switch element having a first end receiving the power supply voltage, and a second end; a second switch element having a first end connected to the second end of the first switch element and a second end via which the first boosted voltage is output; and a capacitor having a first end connected to the second end of the first switch element and a second end receiving a driving signal.

Claim 5

The semiconductor memory device as claimed in claim 2, wherein the second circuit section comprises: a first switch element having a first end receiving the power supply voltage and a second end; a second switch element having a first end connected to the second end of the first switch element and a second end; a third switch element having a first end connected to the second end of the second switch element and a second end via which the second boosted voltage is output; a first capacitor having a first end connected to the second end of the first switch element and a second end receiving a first driving signal; and a second capacitor having a first end connected to the second end of the second switch element and a second end receiving a second driving signal having a complementary relationship with the first driving signal.

Claim 6

The semiconductor memory device as claimed in claim 2, wherein said first circuit section comprises: a first switch element having a first end receiving the power supply voltage, and a second end; a second switch element having a first end connected to the second end of the first switch element and a second end via which the first boosted voltage is output; and a first capacitor having a first end connected to the second end of the first switch element and a second end receiving a first driving signal, and wherein the second circuit section comprises: a third switch element having a first end receiving the power supply voltage and a second end; a fourth switch element having a first end connected to the second end of the third switch element and a second end; a fifth switch element having a first end connected to the second end of the fourth switch element and a second end via which the second boosted voltage is output; a second capacitor having a first end connected to the second end of the third switch element and a second end receiving a second driving signal; and a third capacitor having a first end connected to the second end of the fourth switch element and a second end receiving a third driving signal having a complementary relationship with the second driving signal.

Claim 7

The semiconductor memory device as claimed in claim 5, wherein the first driving signal is the same as the second driving signal.

Claim 8

The semiconductor memory device as claimed in claim 5, further comprising an oscillation circuit generating the second and third driving signals.

Claim 9

The semiconductor memory device as claimed in claim 5, further comprising an oscillation circuit generating the second and third driving signals, wherein the first driving signal is based on a row address strobe signal externally applied to the semiconductor memory device.

Claim 10

A semiconductor memory device comprising a boost circuit that produces boosted voltages from a power supply voltage, said boosted voltages having different voltage values, wherein said boost circuit includes a plurality of boost circuits, wherein the plurality of boost circuits includes a first boost circuit that produces a first boosted voltage to be supplied to word lines for selecting memory cells and circuits which connect bit lines serving as data transfer paths to sense amplifiers, and a second boost circuit that produces a second boosted voltage to be supplied to a circuit which precharges the bit lines, wherein the second boosted voltage is lower than the first boosted voltage, wherein the first boost circuit includes: a first switch element having a first end supplied to the power supply voltage, and a second end; a second switch element having a first end connected to the second end of the first switch element, and a second end; a third switch element having a first end connected to the second end of the second switch element, and a second end via which the first boosted voltage is output; a first capacitor having a first end connected between the first and second switch elements, and a second end supplied with a first driving signal; and a second capacitor having a first end connected between the second and third switch elements, and a second end supplied with a second driving signal which corresponds to an inverted version of the first driving signal, and wherein said second boost circuit includes: a fourth switch element having a first end supplied with the power supply voltage, and a second end; a fifth switch element having a first end connected to the second end of the fourth switch element, and a second end via which the second boosted voltage is output; and a third capacitor having a first end connected between the fourth and fifth switch elements, and a second end supplied with a third driving signal.

Claim 11

A semiconductor memory device comprising a boost circuit that produces boosted voltages from a power supply voltage, said boosted voltages having different voltage values, wherein said boost circuit includes a plurality of boost circuits, wherein the plurality of boost circuits includes a first boost circuit that produces a first boosted voltage to be supplied to word lines for selecting memory cells and circuits which connect bit lines serving as data transfer paths to sense amplifiers, and a second boost circuit that produces a second boosted voltage to be supplied to a circuit which precharges the bit lines, wherein the second boosted voltage is lower than the first boosted voltage, wherein the first boost circuit includes: a first switch element having a first end supplied to the power supply voltage, and a second end; a second switch element having a first end connected to the second end of the first switch element, and a second end; a third switch element having a first end connected to the second end of the second switch element, and a second end via which the first boosted voltage is output; a first capacitor having a first end connected between the first and second switch elements, and a second end supplied with a first driving signal; and a second capacitor having a first end connected between the second and third switch elements, and a second end supplied with a second driving signal which corresponds to an inverted version of the first driving signal, and wherein said second boost circuit includes: a fourth switch element having a first end supplied with the power supply voltage, and a second end; a fifth switch element having a first end connected to the second end of the fourth switch element, and a second end via which the second boosted voltage is output; and a third capacitor having a first end connected between the fourth and fifth switch elements, and a second end supplied with a third driving signal.

Claim 12

The semiconductor memory device as claimed in claim 9, wherein: the first and second driving signals are signals generated in the semiconductor memory device; and the third driving signal is based on a row address strobe signal supplied from an outside of the semiconductor memory device.

Claim 13

A semiconductor memory device comprising: pairs of bit lines; word lines; first circuits which are respectively coupled to the pairs of the bit lines and precharge the pairs of bit lines in accordance with a first control signal; sense amplifiers respectively coupled to the pair of bit lines; a second circuit which selectively drives the word lines by a second control signal; and a third circuit which produces first and second boosted voltages from a power supply voltage and supplies the first and second boosted voltages to the first and second circuits, respectively, wherein the first control signal is produced from the first boosted voltage and the second control signal is produced from the second boosted voltage, wherein the first boosted voltage is lower than the second boosted voltage.

Claim 14

A semiconductor memory device comprising: pairs of bit lines; word lines; first circuits which are respectively coupled to the pairs of the bit lines and precharge the pairs of bit lines in accordance with a first control signal; sense amplifiers respectively coupled to the pair of bit lines; a second circuit which selectively drives the word lines by a second control signal; and a third circuit which produces first and second boosted voltages from a power supply voltage and supplies the first and second boosted voltages to the first and second circuits, respectively, wherein the first control signal is produced from the first boosted voltage and the second control signal is produced from the second boosted voltage, wherein the first boosted voltage is lower than the second boosted voltage.

Claim 15

The semiconductor memory device as claimed in claim 11, wherein the third circuit includes a first circuit sections which derives the first boosted voltage from the power supply voltage, and a second circuit section which derives the second boosted voltage from the power supply voltage.

Claim 16

The semiconductor memory device as claimed in claim 12, wherein said first circuit section includes: a first switch element having a first end receiving the power supply voltage, and a second end; a second switch element having a first end connected to the second end of the first switch element and a second end via which the first boosted voltage is output; and a capacitor having a first and connected to the second end of the first switch element and a second end receiving a driving signal.

Claim 17

The semiconductor memory device as claimed in claim 12, wherein the second circuit section includes: a first switch element having a first end receiving the power supply voltage and a second end; a second switch element having a first end connected to the second end of the first switch element and a second end; a third switch element having a first end connected to the second end of the second switch element and a second end via which the second boosted voltage is output; a first capacitor having a first end connected to the second end of the first switch element and a second end receiving a first driving signal; and a second capacitor having a first end connected to the second end of the second switch element and a second end receiving a second driving signal having a complementary relationship with the first driving signal.

Claim 18

The semiconductor memory device as claimed in claim 12, wherein said first circuit section includes: a first switch element having a first end receiving the power supply voltage, and a second end; a second switch element having a first end connected to the second end of the first switch element and a second end via which the first boosted voltage is output; and a first capacitor having a first end connected to the second end of the first switch element and a second end receiving a first driving signal, and wherein the second circuit section includes: a third switch element having a first end receiving the power supply voltage and a second end; a fourth switch element having a first end connected to the second end of the fourth switch element and a second end via which the second boosted voltage is output; a second capacitor having a first end connected to the second end of the third switch element and a second end receiving a second driving signal; and a third capacitor having a first end connected to the second end of the fourth switch element and a second end receiving a third driving signal having a complementary relationship with the second driving signal.

Claim 19

The semiconductor memory device as claimed in claim 15, wherein the first driving signal is the same as the second driving signal.

Claim 20

The semiconductor memory device as claimed in claim 15, further comprising an oscillation circuit generating the second and third driving signals.

Claim 21

The semiconductor memory device as claimed in claim 15, further comprising an oscillation circuit generating the second and third driving signals, wherein the first driving signal is based on a row address strobe signal externally applied to the semiconductor memory device.

Claim 22

A semiconductor memory device comprising: a precharge circuit; a transfer circuit; at least two different boosting circuits respectively coupled to the precharge circuit and the transfer circuit so as to apply different voltages to the precharge circuit and the transfer circuit.

Claim 23

A semiconductor memory device comprising: a precharge circuit; a transfer circuit; at least two different boosting circuits respectively coupled to the precharge circuit and the transfer circuit so as to apply different voltages to the precharge circuit and the transfer circuit.