Abstract A power on reset circuit includes a transistor connected between a power supply node and a first node, a first capacitor connected between a ground node and a first node, a resistance element connected parallel to the first capacitor, a first CMOS inverter circuit having an input node connected to the first node and an output node connected to the second node, and a second CMOS inverter circuit having an input node connected to the second node and an output node connected to the first node. Preferably, the power on reset circuit further includes a second capacitor connected between the power supply node and the second node. In the power on reset circuit, when the power is turned off, the first capacitor is fully discharged by the resistance element. Therefore, a reset signal for initializing internal circuitry can be surely generated even when the power is again turned on.
Inventors
👤 Masayuki Iketani
👤 Shigeki Ohbayashi
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-08 15:18
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
88 words
A power on reset circuit, comprising: load means connected between a first power supply node and a first node; a first capacitor connected between a second power supply node and said first node; resistance means connected parallel to said first capacitor; a first CMOS inverter circuit having an input node connected to said first node and an output node connected to a second node; and a second CMOS inverter circuit having an input node connected to said second node and an output node connected to said first node.
Claim 2
Dependent Claim
88 words
A power on reset circuit, comprising: load means connected between a first power supply node and a first node; a first capacitor connected between a second power supply node and said first node; resistance means connected parallel to said first capacitor; a first CMOS inverter circuit having an input node connected to said first node and an output node connected to a second node; and a second CMOS inverter circuit having an input node connected to said second node and an output node connected to said first node.
Claim 3
Dependent Claim
25 words
The power on reset circuit according to claim 1, further comprising a second capacitor connected between said first power supply node and said second node.
Claim 4
Dependent Claim
18 words
The power on reset circuit according to claim 2, wherein said load means includes a diode-connected bipolar transistor.
Claim 5
Dependent Claim
50 words
The power on reset circuit according to claim 2, wherein said load means includes a plurality of load elements connected parallel to each other, and a plurality of fuse elements corresponding to said plurality of load elements, each connected in series to corresponding one of said plurality of load elements.