US5701494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor with multiple supervisor interrupt processing function
Assignee: Renesas Electronics Corp
•
Filing: 1996-05-24
•
Granted: 1997-12-23
•
Expires: 2016-05-24
Abstract
Abstract A microprocessor includes an interrupt request receiving circuit, a reception control section for controlling the interrupt request receiving circuit to receive an interrupt request in response to a reception control signal, and a control section for setting a supervisor interrupt mode when a supervisor interrupt request is received by the interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received. At that time, the reception control signal is issued to the reception control section such that the reception control section inhibits the interrupt request receiving circuit from receiving any supervisor interrupt request in the supervisor interrupt mode, and such that the reception control section permits the interrupt request receiving section to receive any user interrupt request in the supervisor interrupt mode. A user interrupt mode is set when a user interrupt request is received by the interrupt request receiving circuit in the supervisor interrupt mode. In the user interrupt mode, the reception control signal is issued to the reception control section such that the reception control section permits the interrupt request receiving circuit to receive any supervisor interrupt request and another user interrupt request in the user interrupt mode.
Inventors
- 👤 Shuji Satoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
182 words
A microprocessor comprising: an interrupt request receiving circuit; reception control means for controlling said interrupt request receiving circuit to receive an interrupt request in response to a reception control signal; and control means for setting a supervisor interrupt mode when a supervisor interrupt request is received by said interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received, to issue the reception control signal to said reception control means such that said reception control means inhibits said interrupt request receiving circuit from receiving any supervisor interrupt request in the supervisor interrupt mode, and such that said reception control means permits said interrupt request receiving means to receive any user interrupt request in the supervisor interrupt mode, and for setting a user interrupt mode when a user interrupt request is received by said interrupt request receiving circuit in the supervisor interrupt mode, to issue the reception control signal such that said reception control means permits said interrupt request receiving circuit to receive any supervisor interrupt request and another user interrupt request in the user interrupt mode.
Claim 2
Dependent Claim
182 words
A microprocessor comprising: an interrupt request receiving circuit; reception control means for controlling said interrupt request receiving circuit to receive an interrupt request in response to a reception control signal; and control means for setting a supervisor interrupt mode when a supervisor interrupt request is received by said interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received, to issue the reception control signal to said reception control means such that said reception control means inhibits said interrupt request receiving circuit from receiving any supervisor interrupt request in the supervisor interrupt mode, and such that said reception control means permits said interrupt request receiving means to receive any user interrupt request in the supervisor interrupt mode, and for setting a user interrupt mode when a user interrupt request is received by said interrupt request receiving circuit in the supervisor interrupt mode, to issue the reception control signal such that said reception control means permits said interrupt request receiving circuit to receive any supervisor interrupt request and another user interrupt request in the user interrupt mode.
Claim 3
Dependent Claim
80 words
A microprocessor according to claim 1, wherein said control means further comprises means for holding the user interrupt mode when the other user interrupt request is received by said interrupt request receiving circuit in the user interrupt mode set after the supervisor interrupt mode, to issue the reception control signal such that said reception control means permits said interrupt request receiving circuit to receive the other supervisor interrupt request and further another user interrupt request in the user interrupt mode.
Claim 4
Dependent Claim
73 words
A microprocessor according to claim 2, wherein said control means further comprises means for setting the supervisor interrupt mode when the other supervisor interrupt request is received by said interrupt request receiving circuit in the user interrupt mode set after the supervisor interrupt mode, to issue the reception control signal to said reception control means such that said reception control means inhibits said interrupt request receiving circuit from receiving any supervisor interrupt request.
Claim 5
Dependent Claim
75 words
A microprocessor according to claim 3, wherein said control means further comprises: detecting means for detecting a nest level of the supervisor interrupt request; and means for issuing the reception control signal to said reception control means such that said reception control means inhibits said interrupt request receiving circuit from receiving any interrupt request when it is detected by said detecting means that the nest level of the supervisor interrupt request is a predetermined level.
Claim 6
Dependent Claim
151 words
A microprocessor according to claim 1, wherein said control means comprises: supervisor mode signal generating means for generating a signal for setting the supervisor mode in response to the reception of the supervisor interrupt request signal by said interrupt request receiving circuit; masking means for selectively masking the supervisor mode setting signal in accordance with a preset data; and permission/inhibition means for outputting the reception control signal to said interrupt request receiving circuit to inhibit said interrupt request receiving circuit from receiving any supervisor interrupt request when the supervisor mode setting signal is not masked, to permit said interrupt request receiving means to receive any user interrupt request when the supervisor mode setting signal is masked, and to permits said interrupt request receiving circuit to receive any supervisor interrupt request and another user interrupt request when the supervisor mode setting signal is not masked and the user interrupt request is received.
Claim 7
Dependent Claim
77 words
A microprocessor according to claim 5, wherein said control means further comprises: supervisor request counter means for counting the number of received supervisor interrupt requests to detect a nest level of each of the received supervisor interrupts request; and maximum nest level detecting means for detecting whether the detected nest level is equal to a predetermined nest level, and for controlling said permission/inhibition means to inhibit said interrupt request receiving circuit from receiving any supervisor interrupt request.
Claim 8
Dependent Claim
128 words
A microprocessor according to claim 1, wherein a monitor program is executed in the supervisor mode and a user interrupt processing routine is executed in response to the corresponding user interrupt request, and wherein said microprocessor further comprises first and second stacks, and wherein said control means pushes a program counter and program status word of a program being currently executed on said first stack when the supervisor interrupt request is received by said interrupt request receiving circuit or the user interrupt request is first received in the supervisor mode, and said control means pushes a program counter and program status word of a program being currently executed on said second stack when the user interrupt request is received in the user interrupt mode after the supervisor mode.
Claim 9
Dependent Claim
62 words
A microprocessor according to claim 7, wherein said control means pushes a program counter and program status word of a program being currently executed on said first stack in place of the latest pushed program counter and program status word on said first stack when the supervisor interrupt request of a predetermined nest level is received by said interrupt request receiving circuit.
Claim 10
Independent Claim
103 words
A method of controlling reception of an interrupt request in a microprocessor, comprising the steps setting a supervisor interrupt mode when a supervisor interrupt request is received by said interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received; inhibiting reception of any supervisor interrupt request in the supervisor interrupt mode; selectively permitting reception of any user interrupt request in the supervisor interrupt mode in accordance with a preset reception control data to set a user interrupt mode; and permitting reception of any supervisor interrupt request and another user interrupt request in the user interrupt mode.
Claim 11
Independent Claim
103 words
A method of controlling reception of an interrupt request in a microprocessor, comprising the steps setting a supervisor interrupt mode when a supervisor interrupt request is received by said interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received; inhibiting reception of any supervisor interrupt request in the supervisor interrupt mode; selectively permitting reception of any user interrupt request in the supervisor interrupt mode in accordance with a preset reception control data to set a user interrupt mode; and permitting reception of any supervisor interrupt request and another user interrupt request in the user interrupt mode.
Claim 12
Dependent Claim
55 words
A method according to claim 9, further comprising the steps of: holding the user interrupt mode when the other user interrupt request is received in the user interrupt mode set after the supervisor interrupt mode; and permitting reception of the other supervisor interrupt request and further another user interrupt request in the user interrupt mode.
Claim 13
Dependent Claim
43 words
A method according to claim 10, further comprising the steps of: setting the supervisor interrupt mode when the other supervisor interrupt request is received in the user interrupt mode set after the supervisor interrupt mode; and inhibiting reception of any supervisor interrupt request.
Claim 14
Dependent Claim
44 words
A method according to claim 11, further comprising the steps of: detecting a nest level of the supervisor interrupt request; and inhibiting reception of any interrupt request when it is detected that the nest level of the supervisor interrupt request is a predetermined level.
Claim 15
Dependent Claim
60 words
A method according to claim 9, wherein said step of a supervisor mode includes generating a signal for setting the supervisor mode in response to the reception of the supervisor interrupt request signal, and wherein said step of permitting reception of any user interrupt request includes selectively masking the supervisor mode setting signal in accordance with the reception control data.
Claim 16
Dependent Claim
53 words
A method according to claim 9, further comprising the steps of: counting the number of received supervisor interrupt requests to detect a nest level of each of the received supervisor interrupts request; detecting whether the detected nest level is equal to a predetermined nest level; and inhibiting reception of any supervisor interrupt request.
Claim 17
Dependent Claim
113 words
A method according to claim 9, wherein a monitor program is executed in the supervisor mode and a user interrupt processing routine is executed in response to the corresponding user interrupt request, and wherein said method further comprises the steps of: pushing a program counter and program status word of a program being currently executed on said first stack when the supervisor interrupt request is received or the user interrupt request is first received in the supervisor mode; and pushing a program counter and program status word of a program being currently executed on said second stack when the user interrupt request is received in the user interrupt mode after the supervisor mode.
Claim 18
Dependent Claim
57 words
A method according to claim 15, further comprising the steps of: pushing a program counter and program status word of a program being currently executed on said first stack in place of the latest pushed program counter and program status word on said first stack when the supervisor interrupt request of a predetermined nest level is received.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |