US5701442A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of modifying an instruction set architecture of a computer processor to maintain backward compatibility
Assignee: Intel Corp
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Filing: 1995-09-19
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Granted: 1997-12-23
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Expires: 2015-09-19
Abstract
Abstract A method of processor architecture modification includes the step of defining an instruction set architecture for a current generation processor. Reserved within this definition are a set of instructions which perform no-operations (NOPs), have no attached semantics, and do not change any architectural state of the processor. Software code, compatible with the instruction set architecture, is then written for running on the processor. In a next-generation processor, new functionality is added by defining a semantic for one of the NOPs so that programs which utilize the new instruction run on both the current-generation and the next-generation processors.
Inventors
- 👤 Ronny Ronen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30003; G06F9/30076
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
134 words
A method of processor architecture modification comprising the steps of: (a) defining an instruction set architecture (ISA) for a current generation processor which includes a plurality of no-operation instructions (NOPs) having no associated semantics, and wherein execution of any one of the NOPs does not alter an architectural state of the processor; (b) waiting until software programs have been written that are compatible with the ISA and which run on the current generation processor; (c) defining, for at least one of the NOPs, an associated semantic that implements a new instruction in a next generation processor, the next generation processor being an improvement of the current generation processor, such that a new software program that uses the new instruction and which runs on the next generation processor, also runs on the current generation processor.
Claim 2
Independent Claim
134 words
A method of processor architecture modification comprising the steps of: (a) defining an instruction set architecture (ISA) for a current generation processor which includes a plurality of no-operation instructions (NOPs) having no associated semantics, and wherein execution of any one of the NOPs does not alter an architectural state of the processor; (b) waiting until software programs have been written that are compatible with the ISA and which run on the current generation processor; (c) defining, for at least one of the NOPs, an associated semantic that implements a new instruction in a next generation processor, the next generation processor being an improvement of the current generation processor, such that a new software program that uses the new instruction and which runs on the next generation processor, also runs on the current generation processor.
Claim 3
Dependent Claim
15 words
The method according to claim 1 wherein each of the NOPs has a unique opcode.
Claim 4
Dependent Claim
14 words
The method according to claim 2 wherein the plurality of NOPs comprise eight NOPs.
Claim 5
Dependent Claim
23 words
The method according to claim 3 wherein the unique opcodes of the eight NOPs are represented in hexadecimal notation as 0X0F18 to 0X0F1F.
Claim 6
Dependent Claim
100 words
An architecture for a processor which defines a set of instructions that can be incorporated into a program for execution on the processor, the set of instructions including a plurality of no-operation instructions (NOPs), each having a unique opcode and no associated semantics, and wherein execution of any one of the NOPs does not alter an architectural state of the processor; the NOPs being available for use in an improved version of the processor, wherein definition of an associated semantic for at least one of the NOPs in the improved version implements a new instruction that specifies a new operation.
Claim 7
Dependent Claim
100 words
An architecture for a processor which defines a set of instructions that can be incorporated into a program for execution on the processor, the set of instructions including a plurality of no-operation instructions (NOPs), each having a unique opcode and no associated semantics, and wherein execution of any one of the NOPs does not alter an architectural state of the processor; the NOPs being available for use in an improved version of the processor, wherein definition of an associated semantic for at least one of the NOPs in the improved version implements a new instruction that specifies a new operation.
Claim 8
Dependent Claim
20 words
The architecture of claim 5 wherein the new operation alters the architectural state of the improved version of the processor.
Claim 9
Dependent Claim
13 words
The architecture of claim 5 wherein the plurality of NOPs comprise eight NOPs.
Claim 10
Dependent Claim
22 words
The architecture of claim 7 wherein the unique opcodes of the eight NOPs are represented in hexadecimal notation as 0X0F18 to 0X0F1F.
Claim 11
Dependent Claim
31 words
The architecture of claim 5 wherein the new instruction can be incorporated into newly-generated code that is able to run on both the processor and the improved version of the processor.
Claim 12
Dependent Claim
107 words
A processor having an architecture which defines a set of instructions that can be incorporated into a program for execution thereon, the set of instructions including a plurality of no-operation instructions (NOPs), each having a unique opcode and no associated semantics, and wherein execution of any one of the NOPs does not alter an architectural state of the processor; the processor being operable to execute code which includes a new instruction, the code also being executable on a next-generation processor having a new architecture which includes the set of instructions, but with an associated semantic that implements the new instruction for at least one of the NOPs.
Claim 13
Dependent Claim
107 words
A processor having an architecture which defines a set of instructions that can be incorporated into a program for execution thereon, the set of instructions including a plurality of no-operation instructions (NOPs), each having a unique opcode and no associated semantics, and wherein execution of any one of the NOPs does not alter an architectural state of the processor; the processor being operable to execute code which includes a new instruction, the code also being executable on a next-generation processor having a new architecture which includes the set of instructions, but with an associated semantic that implements the new instruction for at least one of the NOPs.
Claim 14
Dependent Claim
19 words
The processor of claim 10 wherein execution of the new instruction alters the architectural state of the next-generation processor.
Claim 15
Dependent Claim
13 words
The processor of claim 10 wherein the plurality of NOPs comprise eight NOPs.
Claim 16
Dependent Claim
22 words
The processor of claim 12 wherein the unique opcodes of the eight NOPs are represented in hexadecimal notation as 0X0F18 to 0X0F1F.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |