Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer

Claim 2

A contact, for a semiconductor device, comprising a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer so as to form a junction therebetween, the second semiconductor layer having a lower surface adjacent the first semiconductor later and side surfaces extending from the lower surface in a direction away from the first semiconductor layer, and impurity-doped third semiconductor layers positioned such that the first semiconductor layer is between the third semiconductor layers, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, the third semiconductor layers being in electrical contact with the first semiconductor layer and physically contacting opposed sides of the first semiconductor layer, said third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 3

A contact according to claim 1, further comprising an electrically conducting member overlying the second semiconductor layer such that the second semiconductor layer is between the conducting member and the first semiconductor member.

Claim 4

A contact according to claim 1, wherein the first and second semiconductor layers are made of different semiconductor materials, a hetero-junction being formed between the first and second semiconductor layers.

Claim 5

A contact according to claim 3, wherein the first and second semiconductor layers are each made of III-V semiconductor material.

Claim 6

A semiconductor device comprising the contact of claim 1, the semiconductor device including the first and second semiconductor layers.

Claim 7

A contact according to claim 1, wherein said third semiconductor layers physically contact the lower surface of the second semiconductor layer but do not physically contact the side surfaces of the second semiconductor layer.

Claim 8

A contact according to claim 1, wherein the second semiconductor layer has corners formed by the side surfaces and the lower surface, at a location where the side surfaces begin to extend away from the lower surface, and wherein said third semiconductor layers physically contact said corners but do not physically contact the side surfaces of the second semiconductor layer.

Claim 9

A semiconductor device comprising at least one field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and being of a different semiconductor material than that of the first semiconductor layer so as to form a hetero-junction between the first and second semiconductor layers, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, a gate electrode overlying the second semiconductor layer, a channel being formed in the first semiconductor layer under the gate electrode, third semiconductor layers at opposed sides of the first semiconductor layer, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, the third semiconductor layers being impurity-doped, and source and drain electrodes respectively in contact with the third semiconductor layers, wherein the third semiconductor layers are in physical contact with the opposed sides of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 10

A semiconductor device comprising at least one field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and being of a different semiconductor material than that of the first semiconductor layer so as to form a hetero-junction between the first and second semiconductor layers, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, a gate electrode overlying the second semiconductor layer, a channel being formed in the first semiconductor layer under the gate electrode, third semiconductor layers at opposed sides of the first semiconductor layer, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, the third semiconductor layers being impurity-doped, and source and drain electrodes respectively in contact with the third semiconductor layers, wherein the third semiconductor layers are in physical contact with the opposed sides of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 11

A semiconductor device according to claim 8, wherein each of the first, second and third semiconductor layers is made of III-V semiconductor material.

Claim 12

A semiconductor device according to claim 8, wherein the first and third semiconductor layers are made of a same semiconductor material, different from the semiconductor material of the second semiconductor layer.

Claim 13

A semiconductor device according to claim 10, wherein the first and third semiconductor layers are made of GaAs, and the second semiconductor layer is made of AlGaAs.

Claim 14

A semiconductor device according to claim 10, wherein the first and third semiconductor layers are made of InGaAs, and the second semiconductor layer is made of AlGaAs.

Claim 15

A semiconductor device according to claim 10, wherein the first and third semiconductor layers are made of InGaAs, and the second semiconductor layer is made of InAlAs.

Claim 16

A semiconductor device according to claim 8, wherein the gate electrode includes a first gate electrode member overlying the second semiconductor layer and a second gate electrode member in electrical contact with and overlying the first gate electrode member, the second gate electrode member being made of a material having lower resistivity than material of the first gate electrode member.

Claim 17

A semiconductor device according to claim 14, wherein the material of the second gate electrode member is aluminum, and the material of the first gate electrode member is a WSi/W laminate.

Claim 18

A semiconductor device according to claim 8, wherein the device has at least two of the field-effect transistors, on a single substrate, one of the at least two field-effect transistors having third semiconductor layers that are doped with an n-type impurity so as to form n-type third semiconductor layers, and another of the at least two field-effect transistors having third semiconductor layers that are doped with p-type impurity so as to form p-type third semiconductor layers, said one and said another of the at least two field-effect transistors providing complementary transistors on the single substrate.

Claim 19

A semiconductor device according to claim 8, wherein the first semiconductor layer, in which the channel is formed, has a delta-doped layer therein.

Claim 20

A semiconductor device according to claim 17, wherein the delta-doped layer is a silicon delta-doped layer.

Claim 21

A semiconductor device according to claim 8, wherein said second semiconductor layer is a barrier layer.

Claim 22

A semiconductor device according to claim 8, wherein a length of the gate electrode is substantially the same as a length between the third semiconductor layers in contact with the opposed sides of the first semiconductor layer.

Claim 23

A semiconductor device according to claim 8, wherein said third semiconductor layers physically contact the lower surface of the second semiconductor layer but do not physically contact the side surfaces of the second semiconductor layer.

Claim 24

A semiconductor device according to claim 8, wherein the second semiconductor layer has corners formed by the side surfaces and the lower surface, at a location where the side surfaces begin to extend away from the lower surface, and wherein said third semiconductor layers physically contact said corners but do not physically contact the side surfaces of the second semiconductor layer.

Claim 25

A semiconductor device comprising a field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having an electron affinity which is smaller than that of the first semiconductor layer, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, and a gate electrode formed on the second semiconductor layer, wherein the first semiconductor layer is arranged between third semiconductor layers to which n-type impurities have been added, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, and the third semiconductor layers are connected to source and drain electrodes, the third semiconductor layers being in physical contact with side surfaces of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 26

A semiconductor device comprising a field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having an electron affinity which is smaller than that of the first semiconductor layer, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, and a gate electrode formed on the second semiconductor layer, wherein the first semiconductor layer is arranged between third semiconductor layers to which n-type impurities have been added, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, and the third semiconductor layers are connected to source and drain electrodes, the third semiconductor layers being in physical contact with side surfaces of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 27

A semiconductor device according to claim 23, wherein the first semiconductor layer is GaAs, the second semiconductor layer is AlGaAs, and the third semiconductor layers are GaAs.

Claim 28

A semiconductor device according to claim 23, wherein the first semiconductor layer is InGaAs, the second semiconductor layer is AlGaAs, and the third semiconductor layers are InGaAs.

Claim 29

A semiconductor device according to claim 23, wherein the first semiconductor layer is InGaAs, the second semiconductor layer is InAlAs, and the third semiconductor layers are InGaAs.

Claim 30

A semiconductor device according to claim 23, wherein the first semiconductor layer is of n-type conductivity.

Claim 31

A semiconductor device according to claim 27, wherein the second semiconductor layer is of n-type conductivity.

Claim 32

A semiconductor device according to claim 27, wherein the second semiconductor layer is undoped.

Claim 33

A semiconductor device according to claim 23, wherein the second semiconductor layer contains n-type impurities.

Claim 34

A semiconductor device according to claim 30, wherein the first semiconductor layer is substantially undoped.

Claim 35

A semiconductor device according to claim 23, wherein both the first and second semiconductor layers are substantially undoped.

Claim 36

A semiconductor device according to claim 23, wherein a length of the gate electrode is substantially the same as a length between the third semiconductor layers in contact with the opposed sides of the first semiconductor layer.

Claim 37

A semiconductor device according to claim 23, wherein said third semiconductor layers physically contact the lower surface of the second semiconductor layer but do not physically contact the side surfaces of the second semiconductor layer.

Claim 38

A semiconductor device according to claim 23, wherein the second semiconductor layer has corners formed by the side surfaces and the lower surface, at a location where the side surfaces begin to extend away from the lower surface, and wherein said third semiconductor layers physically contact said corners but do not physically contact the side surfaces of the second semiconductor layer.

Claim 39

A semiconductor device comprising a field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, each of the first and second semiconductor layers having a sum of an electron affinity and a band gap, the sum being larger for the second semiconductor layer than for the first semiconductor layer, and a gate electrode formed on the second semiconductor layer, wherein the first semiconductor layer is arranged between third semiconductor layers to which p-type impurities have been added, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, and the third semiconductor layers are connected to source and drain electrodes, the third semiconductor layers being in physical contact with side surfaces of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 40

A semiconductor device comprising a field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, each of the first and second semiconductor layers having a sum of an electron affinity and a band gap, the sum being larger for the second semiconductor layer than for the first semiconductor layer, and a gate electrode formed on the second semiconductor layer, wherein the first semiconductor layer is arranged between third semiconductor layers to which p-type impurities have been added, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, and the third semiconductor layers are connected to source and drain electrodes, the third semiconductor layers being in physical contact with side surfaces of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.

Claim 41

A semiconductor device according to claim 36, wherein the first semiconductor layer is GaAs, the second semiconductor layer is AlGaAs, and the third semiconductor layers are GaAs.

Claim 42

A semiconductor device according to claim 36, wherein the first semiconductor layer is InGaAs, the second semiconductor layer is AlGaAs, and the third semiconductor layers are InGaAs.

Claim 43

A semiconductor device according to claim 36, wherein the first semiconductor layer is InGaAs, the second semiconductor layer is InAlAs, and the third semiconductor layers are InGaAs.

Claim 44

A semiconductor device according to claim 36, wherein the first semiconductor layer is of p-type conductivity.

Claim 45

A semiconductor device according to claim 40, wherein the second semiconductor layer is of p-type conductivity.

Claim 46

A semiconductor device according to claim 40, wherein the second semiconductor layer is substantially undoped.

Claim 47

A semiconductor device according to claim 36, wherein the second semiconductor layer contains p-type impurities.

Claim 48

A semiconductor device according to claim 43, wherein the first semiconductor layer is substantially undoped.

Claim 49

A semiconductor device according to claim 36, wherein both the first and second semiconductor layers are substantially undoped.

Claim 50

A semiconductor device according to claim 36, wherein a length of the gate electrode is substantially the same as a length between the third semiconductor layers in contact with the opposed sides of the first semiconductor layer.

Claim 51

A semiconductor device according to claim 36, wherein said third semiconductor layers physically contact the lower surface of the second semiconductor layer but do not physically contact the side surfaces of the second semiconductor layer.

Claim 52

A semiconductor device according to claim 36, wherein the second semiconductor layer has corners formed by the side surfaces and the lower surface, at a location where the side surfaces begin to extend away from the lower surface, and wherein said third semiconductor layers physically contact said corners but do not physically contact the side surfaces of the second semiconductor layer.