US5699383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-power linear amplification using periodically updated amplitude and phase correction values
Assignee: NEC Corp
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Filing: 1996-03-06
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Granted: 1997-12-16
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Expires: 2016-03-06
Abstract
Abstract In a high-power transmitter, an input complex signal is multiplied in a complex multiplier by control signals. The output complex signal from the multiplier is converted to a high frequency signal and amplified by a power amplifier for transmission. The amplitude of the input complex signal is detected to access a memory where amplitude and phase correction values are stored. During a read mode of the memory, a set of amplitude and phase correction values is specified by the detected amplitude and supplied to the complex amplifier as the control signals. During a write mode of the memory, a set of amplitude and phase correction values is specified by a delayed version of the detected amplitude and rewritten with a set of new amplitude and phase correction values. The amplified high frequency signal is down-converted to a low frequency complex signal. The nonlinearity of the power amplifier is determined from a delayed version of the input complex signal and the down-converted complex signal and the new amplitude and phase correction values are produced from the detected nonlinearity and delayed versions of the amplitude and phase correction values which were supplied to the complex multiplier. At intervals, the memory is switched from the read mode to the write mode for updating its contents.
Inventors
- 👤 Osamu Ichiyoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:17
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/08; H03F; H03F1/00; H03F1/32; H03F1/3241; H03F1/3247; H03F1/3294; H04; H04L; H04L27/00; H04L27/32; H04L27/34; H04L27/36; H04L27/366; H04L27/367; H04L27/368; H03F2200/00; H03F2200/102; H03F2201/00; H03F2201/32; H03F2201/3233
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
225 words
A transmission apparatus comprising: a complex multiplier for multiplying an input complex signal by control signals and producing a compensated complex signal; an up-converter for converting the compensated complex signal to a high frequency signal; a power amplifier for amplifying the high frequency signal for transmission; an envelope detector for detecting an amplitude of said input complex signal; a memory having a plurality of locations for storing a plurality of sets of amplitude and phase correction values, the memory supplying a set of amplitude and phase correction values from a location specified by the detected amplitude to the complex multiplier as said control signals during a read mode and rewriting a set of amplitude and phase correction values stored in a location specified by a delayed version of the detected amplitude with new amplitude and phase correction values during a write mode; a down-converter for converting the amplified high frequency signal to a low frequency complex signal; nonlinearity detector means for detecting nonlinearity of said power amplifier from a delayed version of the input complex signal and the low frequency complex signal and producing said new amplitude and phase correction values from the detected nonlinearity and delayed versions of the amplitude and phase correction values supplied to said complex multiplier; and means for periodically switching said memory from the read mode to the write mode.
Claim 2
Dependent Claim
225 words
A transmission apparatus comprising: a complex multiplier for multiplying an input complex signal by control signals and producing a compensated complex signal; an up-converter for converting the compensated complex signal to a high frequency signal; a power amplifier for amplifying the high frequency signal for transmission; an envelope detector for detecting an amplitude of said input complex signal; a memory having a plurality of locations for storing a plurality of sets of amplitude and phase correction values, the memory supplying a set of amplitude and phase correction values from a location specified by the detected amplitude to the complex multiplier as said control signals during a read mode and rewriting a set of amplitude and phase correction values stored in a location specified by a delayed version of the detected amplitude with new amplitude and phase correction values during a write mode; a down-converter for converting the amplified high frequency signal to a low frequency complex signal; nonlinearity detector means for detecting nonlinearity of said power amplifier from a delayed version of the input complex signal and the low frequency complex signal and producing said new amplitude and phase correction values from the detected nonlinearity and delayed versions of the amplitude and phase correction values supplied to said complex multiplier; and means for periodically switching said memory from the read mode to the write mode.
Claim 3
Dependent Claim
67 words
A transmission apparatus as claimed in claim 1, wherein the nonlinearity detector means comprises: an error detector for detecting amplitude and phase errors between the delayed version of the input complex signal and the low frequency complex signal; and update means for producing said new amplitude and phase correction values from the amplitude and phase errors and said delayed versions of the amplitude and phase correction values.
Claim 4
Dependent Claim
81 words
A transmission apparatus as claimed in claim 2, wherein the error detector includes means for producing said amplitude and phase errors by a ratio between said delayed version of the input complex signal and the low frequency complex signal to detect said amplitude and phase errors, and wherein said update means includes means for multiplying the delayed version of the amplitude correction value by the amplitude error and subtracting the phase error from the delayed version of the phase correction value.
Claim 5
Dependent Claim
42 words
A transmission apparatus as claimed in claim 2, wherein said update means comprises a memory for converting the delayed versions of the amplitude and phase correction values to said new amplitude and phase correction values according to the amplitude and phase errors.
Claim 6
Dependent Claim
37 words
A transmission apparatus as claimed in claim 1, further comprising a multiplexer for frequency division multiplexing a plurality of signals to produce a frequency-division multiplex signal, and converting the frequency-division multiplex signal to said input complex signal.
Claim 7
Dependent Claim
22 words
A transmission apparatus as claimed in claim 1, wherein said up-converter comprises a quadrature modulator and said down-converter comprises a quadrature demodulator.
Claim 8
Independent Claim
194 words
A method for linearly operating a power amplifier, comprising the steps of: a) detecting an amplitude of an input complex signal; b) reading a set of amplitude and phase correction values from a location of a memory specified by the detected amplitude; c) multiplying the input complex signal by the read amplitude and phase correction values to produce a compensated complex signal; d) converting the compensated complex signal to a high frequency signal and supplying the high frequency signal to the power amplifier; e) converting an output signal of the power amplifier to a low frequency complex signal; f) detecting nonlinearity of said power amplifier from a delayed version of the input complex signal and the low frequency complex signal and producing a set of new amplitude and phase correction values from the detected nonlinearity and delayed versions of the amplitude and phase correction values read by the step (b); and g) rewriting a set of amplitude and phase correction values stored in a location of the memory specified by a delayed version of the amplitude detected by the step (a) with the new amplitude and phase correction values produced by the step (f).
Claim 9
Independent Claim
194 words
A method for linearly operating a power amplifier, comprising the steps of: a) detecting an amplitude of an input complex signal; b) reading a set of amplitude and phase correction values from a location of a memory specified by the detected amplitude; c) multiplying the input complex signal by the read amplitude and phase correction values to produce a compensated complex signal; d) converting the compensated complex signal to a high frequency signal and supplying the high frequency signal to the power amplifier; e) converting an output signal of the power amplifier to a low frequency complex signal; f) detecting nonlinearity of said power amplifier from a delayed version of the input complex signal and the low frequency complex signal and producing a set of new amplitude and phase correction values from the detected nonlinearity and delayed versions of the amplitude and phase correction values read by the step (b); and g) rewriting a set of amplitude and phase correction values stored in a location of the memory specified by a delayed version of the amplitude detected by the step (a) with the new amplitude and phase correction values produced by the step (f).
Claim 10
Dependent Claim
71 words
A method as claimed in claim 7, wherein the step (f) comprises the steps of: f 1 ) detecting amplitude and phase errors between the delayed version of the input complex signal and the low frequency complex signal; and f 2 ) producing said new amplitude and phase correction values from the amplitude and phase errors and delayed versions of the amplitude and phase correction values read by the step (b).
Claim 11
Dependent Claim
86 words
A method as claimed in claim 8, wherein the step (f 1 ) includes the step of producing said amplitude and phase errors by a ratio between said delayed version of the input complex signal and the low frequency complex signal to detect said amplitude and phase errors, and wherein the step (f 2 ) includes the step of multiplying the delayed version of the amplitude correction value by the amplitude error and subtracting the phase error from the delayed version of the phase correction value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |