US5699306A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Row redundancy for nonvolatile semiconductor memories
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-01-29
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Granted: 1997-12-16
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Expires: 2016-01-29
Abstract
Abstract A redundant circuit for EEPROMs which is capable of replacing defective normal memory cells with redundant memory cells in a wafer state as well as in a packaged state. The nonvolatile semiconductor memory includes an array having normal row blocks and redundant row blocks. A normal row decoder selects one of the normal row blocks, and a normal row decoder disable circuit disables the normal row decoder in response to a redundant array selection command. A redundant row block selection circuit selects one of the redundant row blocks in response to the redundant array selection command and an external address. First and second redundant latch circuits are provided for storing programmed addresses corresponding to defective normal row blocks. The second redundant latch circuit is programmed when first redundant row blocks are defective, and is capable of being programmed in a package state. Thereafter, a redundant address overlap selection prevention circuit prevents both the first and second redundant row blocks from being selected when the defective normal row block address is specified, and enables only the second redundant row block to be selected instead.
Inventors
- 👤 Sung-Soo Lee
- 👤 Jin-Ki Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:06
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
179 words
A nonvolatile semiconductor memory comprising: a normal memory cell array having a plurality of normal row blocks; a redundant memory cell array having a plurality of redundant row blocks; a normal row decoder which selects one of said normal row blocks; a redundant row decoder connected to said redundant row blocks; a redundant address latch circuit connected to said redundant row decoder which is programmed with an address specifying a defective normal row block so as to substitute a first redundant row block for said defective normal row block, and when said first redundant row block is defective, said redundant address latch circuit is reprogrammed with said address so as to substitute a second redundant row block for said first redundant row block; a normal row decoder disable circuit which disables said normal row decoder when said defective normal row block is selected; and an overlap selection inhibiting circuit which prevents selection of said first redundant row block when said defective normal row block is selected such that said redundant row decoder instead selects said second redundant row block.
Claim 2
Dependent Claim
179 words
A nonvolatile semiconductor memory comprising: a normal memory cell array having a plurality of normal row blocks; a redundant memory cell array having a plurality of redundant row blocks; a normal row decoder which selects one of said normal row blocks; a redundant row decoder connected to said redundant row blocks; a redundant address latch circuit connected to said redundant row decoder which is programmed with an address specifying a defective normal row block so as to substitute a first redundant row block for said defective normal row block, and when said first redundant row block is defective, said redundant address latch circuit is reprogrammed with said address so as to substitute a second redundant row block for said first redundant row block; a normal row decoder disable circuit which disables said normal row decoder when said defective normal row block is selected; and an overlap selection inhibiting circuit which prevents selection of said first redundant row block when said defective normal row block is selected such that said redundant row decoder instead selects said second redundant row block.
Claim 3
Dependent Claim
39 words
A nonvolatile semiconductor memory according to claim 1, wherein said normal and redundant memory cell arrays include a plurality of memory cells arranged in rows and columns, said normal and redundant row blocks comprising a number of said rows.
Claim 4
Dependent Claim
198 words
A nonvolatile semiconductor memory comprising: a normal memory cell array having a plurality of normal row blocks; a redundant memory cell array having a plurality of redundant row blocks; a normal row decoder which selects one of said normal row blocks; first and second redundant row decoders which select one of said first redundant row blocks and one of said second redundant row blocks, respectively; a first redundant address latch circuit which is programmed with an address specifying a defective normal row block such that said first redundant row decoder selects one of said first redundant row blocks in response to said specified address; a second redundant address latch circuit which is programmed with said specified address such that said second redundant row decoder selects one of said second redundant row blocks in response to said specified address; a normal row decoder disable circuit which disables said normal row decoder when said defective normal row block is selected; and an overlap selection inhibiting circuit which prevents selection of said one of said first redundant row blocks such that said second redundant row decoder selects said one of said second redundant row blocks in response to said specified address.
Claim 5
Dependent Claim
198 words
A nonvolatile semiconductor memory comprising: a normal memory cell array having a plurality of normal row blocks; a redundant memory cell array having a plurality of redundant row blocks; a normal row decoder which selects one of said normal row blocks; first and second redundant row decoders which select one of said first redundant row blocks and one of said second redundant row blocks, respectively; a first redundant address latch circuit which is programmed with an address specifying a defective normal row block such that said first redundant row decoder selects one of said first redundant row blocks in response to said specified address; a second redundant address latch circuit which is programmed with said specified address such that said second redundant row decoder selects one of said second redundant row blocks in response to said specified address; a normal row decoder disable circuit which disables said normal row decoder when said defective normal row block is selected; and an overlap selection inhibiting circuit which prevents selection of said one of said first redundant row blocks such that said second redundant row decoder selects said one of said second redundant row blocks in response to said specified address.
Claim 6
Dependent Claim
39 words
A nonvolatile semiconductor memory according to claim 3, wherein said normal and redundant memory cell arrays include a plurality of memory cells arranged in rows and columns, said normal and redundant row blocks comprising a number of said rows.
Claim 7
Dependent Claim
39 words
A nonvolatile semiconductor memory according to claim 3, wherein said first redundant address latch circuit is programmed in a wafer state, and said second redundant address latch circuit is programmed in a packaged state of said nonvolatile semiconductor memory.
Claim 8
Dependent Claim
23 words
A nonvolatile semiconductor memory according to claim 3, wherein said first and second redundant address latch circuits are programmed in a packaged state.
Claim 9
Independent Claim
93 words
A method of replacing a defective normal row block in a nonvolatile semiconductor memory, comprising the steps of: programming an address specifying said defective normal row block such that a first redundant row block is substituted for said defective normal row block; re-programming said address when said first redundant row block fails such that a second redundant row block is substituted for said first redundant row block; and inhibiting selection of said first redundant row block and enabling selection of said second redundant row block when said defective normal row block is selected.
Claim 10
Independent Claim
93 words
A method of replacing a defective normal row block in a nonvolatile semiconductor memory, comprising the steps of: programming an address specifying said defective normal row block such that a first redundant row block is substituted for said defective normal row block; re-programming said address when said first redundant row block fails such that a second redundant row block is substituted for said first redundant row block; and inhibiting selection of said first redundant row block and enabling selection of said second redundant row block when said defective normal row block is selected.
Claim 11
Dependent Claim
53 words
A method according to claim 7, further comprising the steps of: receiving a redundant array selection command and said address; preventing the selection of said defective normal row block in response to said array selection command; selecting said second redundant row block in response to said redundant array selection command and said address.
References Cited (Backward Citations)
US5457655A
Cited
US5477492A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |